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    SEMICONDUCTOR STRUCTURE
    14.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20220208694A1

    公开(公告)日：2022-06-30

    申请号：US17179422

    申请日：2021-02-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Yu-Ren Wang

    IPC: H01L23/00 ,  H01L29/20

    Abstract: A semiconductor structure includes a substrate including a device region, a peripheral region surrounding the device region, and a transition region disposed between the device region and the peripheral region. An epitaxial layer is disposed on the device region, the peripheral region, and the transition region. A first portion of the epitaxial layer on the peripheral region has a poly-crystal structure.

    HIGH ELECTRON MOBILITY TRANSISTOR
    16.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR 有权

    公开(公告)号：US20210151591A1

    公开(公告)日：2021-05-20

    申请号：US16711451

    申请日：2019-12-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Yu-Chi Wang ,  Tsung-Mu Yang ,  Yu-Ren Wang

    IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205

    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.

    METHOD OF FORMING FINFET DEVICE
    18.
    发明申请
    METHOD OF FORMING FINFET DEVICE 审中-公开

    公开(公告)号：US20190229202A1

    公开(公告)日：2019-07-25

    申请号：US16254397

    申请日：2019-01-22

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Ching-I Li

    IPC: H01L29/66 ,  H01L27/11 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/24 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088

    Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

    FinFET device and method of forming the same
    19.
    发明授权
    FinFET device and method of forming the same 有权

    公开(公告)号：US10263096B1

    公开(公告)日：2019-04-16

    申请号：US15878836

    申请日：2018-01-24

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Ching-I Li

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11 ,  H01L27/088 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L21/8234 ,  H01L21/311

    Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

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