公开(公告)号：US20180337064A1

公开(公告)日：2018-11-22

申请号：US15980902

申请日：2018-05-16

申请人： Atomera Incorporated

发明人： HIDEKI TAKEUCHI

IPC分类号： H01L21/322 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L21/3225 ,  H01L21/02381 ,  H01L21/02507 ,  H01L21/3221 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L29/151 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A semiconductor processing method may include forming a superlattice gettering layer on a front side of a semiconductor substrate having a first thickness, epitaxially growing an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, forming at least one semiconductor device in the active semiconductor layer, and forming at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer into the semiconductor substrate. The method may further include thinning the semiconductor substrate from a back side thereof to a second thickness less than the first thickness, and thinning the semiconductor substrate. The superlattice gettering layer getters metal ions released by the forming of the at least one metal interconnect layer and at least one metal through-via, and thinning the substrate.

公开(公告)号：US20180062031A1

公开(公告)日：2018-03-01

申请号：US15557600

申请日：2016-03-29

申请人： OSRAM Opto Semiconductors GmbH

发明人： Asako Hirai ,  Tobias Meyer ,  Philipp Drechsel ,  Peter Stauß ,  Anna Nirschl ,  Alvaro Gomez-Iglesias ,  Tobias Niebling ,  Bastian Galler

IPC分类号： H01L33/06 ,  H01L31/0352 ,  H01L29/15

CPC分类号： H01L31/0352 ,  H01L29/151 ,  H01L29/152 ,  H01L31/035236 ,  H01L33/06

摘要： An optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure comprises multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction, wherein the multi-quantum-well structure has at least one emission region and multiple transport regions which are arranged sequentially in an alternating manner in a direction perpendicular to the growth direction, wherein at least one of the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission regions, and wherein the quantum-well layers in the transport regions and in the emission regions are oriented perpendicularly to the growth direction with exception of a junction region between adjacent transport regions and emission regions.

公开(公告)号：US20170294514A1

公开(公告)日：2017-10-12

申请号：US15629012

申请日：2017-06-21

申请人： ATOMERA INCORPORATED

发明人： ROBERT J. MEARS

IPC分类号： H01L29/15 ,  H01L29/167 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L29/152 ,  H01L21/02507 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/324 ,  H01L29/151 ,  H01L29/167

摘要： A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

公开(公告)号：US09786744B2

公开(公告)日：2017-10-10

申请号：US15341590

申请日：2016-11-02

申请人： AZURSPACE Solar Power GmbH

发明人： Stephan Lutgen ,  Saad Murad ,  Ashay Chitnis

IPC分类号： H01L29/12 ,  H01L31/0336 ,  H01L23/52 ,  H01L21/338 ,  H01L21/337 ,  H01L21/28 ,  H01L29/205 ,  H01L29/36 ,  H01L29/778 ,  H01L29/872 ,  H01L33/00 ,  H01L29/15 ,  H01L21/02 ,  H01L29/20 ,  H01L29/207 ,  H01L29/10

CPC分类号： H01L29/205 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02579 ,  H01L29/1075 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/36 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/872 ,  H01L33/0025

摘要： An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.

公开(公告)号：US09721790B2

公开(公告)日：2017-08-01

申请号：US15169983

申请日：2016-06-01

申请人： ATOMERA INCORPORATED

发明人： Robert J. Mears ,  Nyles Cody ,  Robert John Stephenson

IPC分类号： H01L21/02 ,  H01L29/15 ,  H01L29/06

CPC分类号： H01L21/02507 ,  H01L21/0245 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/151 ,  H01L29/152

摘要： A method for processing a semiconductor wafer in a single wafer processing chamber may include heating the single wafer processing chamber to a temperature in a range of 650-700° C., and forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Depositing the oxygen may include depositing the oxygen using an N2O gas flow.

公开(公告)号：US09716147B2

公开(公告)日：2017-07-25

申请号：US14734412

申请日：2015-06-09

申请人： ATOMERA INCORPORATED

发明人： Robert J. Mears

IPC分类号： H01L29/06 ,  H01L29/15 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/167

CPC分类号： H01L29/152 ,  H01L21/02507 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/324 ,  H01L29/151 ,  H01L29/167

摘要： A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

公开(公告)号：US20170104132A1

公开(公告)日：2017-04-13

申请号：US15391922

申请日：2016-12-28

申请人： Sensor Electronic Technology, Inc.

发明人： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

IPC分类号： H01L33/32 ,  H01L33/12 ,  H01L33/06 ,  H01L33/00

CPC分类号： H01L33/32 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/151 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/025 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/20

摘要： A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

公开(公告)号：US20160027737A1

公开(公告)日：2016-01-28

申请号：US14789645

申请日：2015-07-01

申请人： The Board of Trustees of the University of Illinois

发明人： John A. ROGERS ,  Dahl-Young KHANG ,  Yugang SUN ,  Etienne MENARD

IPC分类号： H01L23/538 ,  H05K1/02 ,  H01L29/786 ,  H01L23/00

CPC分类号： H01L23/5387 ,  B81C2201/0185 ,  B82Y10/00 ,  H01L21/02422 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02628 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/564 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L27/1266 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/06 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/151 ,  H01L29/158 ,  H01L29/16 ,  H01L29/1602 ,  H01L29/1606 ,  H01L29/7781 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78696 ,  H01L31/0392 ,  H01L31/03925 ,  H01L31/03926 ,  H01L31/18 ,  H01L31/1804 ,  H01L2221/68368 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/80894 ,  H01L2224/8385 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01067 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/10349 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3025 ,  H05K1/0277 ,  H05K1/0283 ,  Y02E10/547 ,  Y02P70/521 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

公开(公告)号：US20160013306A1

公开(公告)日：2016-01-14

申请号：US14858992

申请日：2015-09-18

申请人： QUALCOMM Incorporated

发明人： Xia LI ,  Bin YANG ,  Ming CAI

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/15 ,  H01L29/66 ,  H01L29/205 ,  H01L29/78

CPC分类号： H01L29/7789 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/151 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7781 ,  H01L29/7783 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

摘要： An inner fin of a high bandgap material is on a substrate, having two vertical faces, and is surrounded by a carrier redistribution fin of a low bandgap material. The inner fin and the carrier redistribution fin have two vertical interfaces. The carrier redistribution fin has a thickness and a bandgap relative to the bandgap of the inner fin that establishes, along the two vertical interfaces, an equilibrium of a corresponding two two-dimensional electron gasses.

摘要翻译： 高带隙材料的内翅片在基板上，具有两个垂直面，并被低带隙材料的载流子再分布翅片围绕。 内鳍和载体再分布鳍具有两个垂直接口。 载流子再分布片相对于内鳍的带隙具有厚度和带隙，沿着两个垂直界面建立相应的两个二维电子气体的平衡。

公开(公告)号：US20150357414A1

公开(公告)日：2015-12-10

申请号：US14734412

申请日：2015-06-09

申请人： MEARS Technologies, Inc.

发明人： Robert J. MEARS

IPC分类号： H01L29/15 ,  H01L29/167 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L29/152 ,  H01L21/02507 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/324 ,  H01L29/151 ,  H01L29/167

摘要： A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

摘要翻译： 制造半导体器件的方法可以包括在半导体衬底上形成多个堆叠的层组，其中每组层包括限定基底半导体部分的多个堆叠的基底半导体单层和限定在其中的至少一个非半导体单层 相邻的基底半导体部分的晶格。 该方法还可以包括在半导体衬底中的至少一个局部区域中的多个层叠组下方的半导体衬底内注入掺杂剂，并且执行多个层叠的层和半导体衬底组的退火， 垂直和水平地限制所述至少一个局部区域中的掺杂剂的层。