公开(公告)号：US10468502B2

公开(公告)日：2019-11-05

申请号：US16254397

申请日：2019-01-22

申请人： United Microelectronics Corp.

发明人： Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Ching-I Li

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/24 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088 ,  H01L27/11

摘要： A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

公开(公告)号：US20190229202A1

公开(公告)日：2019-07-25

申请号：US16254397

申请日：2019-01-22

申请人： United Microelectronics Corp.

发明人： Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Ching-I Li

IPC分类号： H01L29/66 ,  H01L27/11 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/24 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088

摘要： A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

公开(公告)号：US10263096B1

公开(公告)日：2019-04-16

申请号：US15878836

申请日：2018-01-24

申请人： United Microelectronics Corp.

发明人： Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Ching-I Li

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11 ,  H01L27/088 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L21/8234 ,  H01L21/311

摘要： A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

公开(公告)号：US09496396B1

公开(公告)日：2016-11-15

申请号：US14961902

申请日：2015-12-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yu-Ming Hsu ,  Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Sheng-Hsu Liu ,  Chieh-Lung Wu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/24 ,  H01L29/08

CPC分类号： H01L29/24 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a gate structure on the substrate; (c) performing a first deposition process to form a first epitaxial layer adjacent to the gate structure and performing a first etching process to remove part of the first epitaxial layer at the same time; and (d) performing a second etching process to remove part of the first epitaxial layer.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：（a）提供衬底; （b）在所述基板上形成栅极结构; （c）执行第一沉积工艺以形成与所述栅极结构相邻的第一外延层，并且执行第一蚀刻工艺以同时去除所述第一外延层的一部分; 和（d）执行第二蚀刻工艺以去除第一外延层的一部分。

公开(公告)号：US10236179B2

公开(公告)日：2019-03-19

申请号：US15099581

申请日：2016-04-14

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Cheng Yen ,  Tsung-Mu Yang ,  Sheng-Hsu Liu ,  Tsang-Hsuan Wang ,  Chun-Liang Kuo ,  Yu-Ming Hsu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L29/66

摘要： A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

公开(公告)号：US20170301536A1

公开(公告)日：2017-10-19

申请号：US15099581

申请日：2016-04-14

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Cheng Yen ,  Tsung-Mu Yang ,  Sheng-Hsu Liu ,  Tsang-Hsuan Wang ,  Chun-Liang Kuo ,  Yu-Ming Hsu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC分类号： H01L21/02 ,  H01L29/66

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02639 ,  H01L29/66795 ,  H01L29/7848

摘要： A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.

公开(公告)号：US20240038844A1

公开(公告)日：2024-02-01

申请号：US17896096

申请日：2022-08-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Liang Kuo ,  Yen-Hsing Chen ,  Yen-Lun Chen ,  Ruei-Hong Shen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC分类号： H01L29/10 ,  H01L29/778 ,  H01L29/66

CPC分类号： H01L29/1033 ,  H01L29/7786 ,  H01L29/66462

摘要： A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

公开(公告)号：US20220344474A1

公开(公告)日：2022-10-27

申请号：US17334837

申请日：2021-05-31

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yu-Ming Hsu ,  Chun-Liang Kuo ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC分类号： H01L29/15 ,  H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

摘要： A superlattice structure includes a substrate. A first superlattice stack is disposed on the substrate. The first superlattice stack includes a first superlattice layer, a second superlattice layer and a third superlattice layer disposed from bottom to top. Three stress relaxation layers respectively disposed between the first superlattice layer and the second superlattice layer, the second superlattice layer and the third superlattice layer and on the third superlattice layer. Each of the stress relaxation layers includes a group III-V compound layer. The thickness of each of the stress relaxation layers should be greater than a relaxation critical thickness.

公开(公告)号：US20180097110A1

公开(公告)日：2018-04-05

申请号：US15281993

申请日：2016-09-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Tsung-Mu Yang ,  Kuang-Hsiu Chen ,  Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Fu-Cheng Yen ,  Chung-Min Tsai

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/7848 ,  H01L21/02057 ,  H01L29/66636 ,  H01L29/66795

摘要： A method for manufacturing a semiconductor structure comprises the following steps. First, a recess is formed in a substrate. At least one wet cleaning process is performed to the recess and the substrate. Then, a baking process is performed to the recess and the substrate in an atmosphere containing H2 gas. After the baking process, a dry cleaning process is performed the recess and the substrate.

公开(公告)号：US09847393B2

公开(公告)日：2017-12-19

申请号：US15286541

申请日：2016-10-05

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yu-Ming Hsu ,  Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Sheng-Hsu Liu ,  Chieh-Lung Wu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC分类号： H01L29/66 ,  H01L29/24 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/24 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device is disclosed. The semiconductor device includes: a substrate, a gate structure on the substrate, a spacer adjacent to the gate structure, an epitaxial layer in the substrate adjacent to two sides of the spacer, and a dislocation embedded within the epitaxial layer. Preferably, the top surface of the epitaxial layer is lower than the top surface of the substrate, and the top surface of the epitaxial layer has a V-shape.