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公开(公告)号：US20240206151A1
公开(公告)日：2024-06-20
申请号：US18545216
申请日：2023-12-19
发明人： Koji SAKUI , Masakazu KAKUMU , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096
摘要： A memory device includes at least one memory array made up of pages and bit lines. Each page includes multiple memory cells connected to a bit line. A plate line is connected to a first gate conductor layer, a source line is connected to an n+ layer, the bit line is connected to an n+ layer, and a word line is connected to a second gate conductor layer. A write operation of holding positive hole groups near a gate insulating layer and an erase operation of removing the positive hole groups are performed by controlling voltages applied to the source line, the bit line, the word line, the plate line, and the bottom line, where the positive hole groups are generated in a channel region of a third semiconductor layer by a gate induced drain leakage current.
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公开(公告)号：US20240179887A1
公开(公告)日：2024-05-30
申请号：US18520130
申请日：2023-11-27
发明人： Nozomu HARADA , Masakazu KAKUMU , Koji SAKUI
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096
摘要： In a memory cell including a first gate insulating layer 5 and a first gate conductor layer 6 surrounding a P layer 3a constituting a lower portion of a pillar-shaped P layer 3 standing on a P layer substrate 1, a second gate insulating layer 9 surrounding a P layer 3b constituting an upper portion of the P layer 3, a second gate conductor layer 10, and N+ layers 11a and 11b at both ends of the P layer 3b and a MOS transistor including a pillar-shaped P layer 3A standing on a P layer substrate 1a connecting to the same P layer substrate 1, a third gate insulating layer 9a surrounding an upper P layer 3ba of the P layer 3A, a third gate conductor layer 10a, and N+ layers 11aa and 11ba at both ends of the P layer 3ba, bottom portions and top portions of the P layer 3 and the P layer 3A are located at substantially the same heights of line A and line C, respectively, in a perpendicular direction, and bottom portions of the P layer 3b and the P layer 3ba are located at substantially the same height of line B.
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公开(公告)号：US20240029775A1
公开(公告)日：2024-01-25
申请号：US18222116
申请日：2023-07-14
发明人： Koji SAKUI , Masakazu KAKUMU , Nozomu HARADA
IPC分类号： G11C11/403 , G11C11/4096 , G11C11/4097 , H10B12/00
CPC分类号： G11C11/403 , G11C11/4096 , G11C11/4097 , H10B12/20
摘要： A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.
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公开(公告)号：US20230320065A1
公开(公告)日：2023-10-05
申请号：US18190511
申请日：2023-03-27
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096
摘要： A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.
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公开(公告)号：US20240321343A1
公开(公告)日：2024-09-26
申请号：US18609198
申请日：2024-03-19
发明人： Koji SAKUI , Yoshihisa IWATA , Masakazu KAKUMU , Nozomu HARADA
IPC分类号： G11C11/4096 , G11C5/06 , G11C11/4094 , H10B12/00
CPC分类号： G11C11/4096 , G11C5/063 , G11C11/4094 , H10B12/20 , H10B12/50
摘要： In a memory device, a page is composed of memory cells arranged in rows, and pages are arranged in columns in plan view on a substrate. Each memory cell has a semiconductor base, a first impurity layer and a second impurity layer at both ends in an extension direction of the semiconductor base, and at least two (first and second) gate conductor layers. The first impurity layer is connected to a source line, the second impurity layer to a bit line, one of the first or second gate conductor layer to a selection gate line, and the other to a plate line. Voltages applied to the source line, bit line, selection gate line, and plate line are controlled to perform page erasing and writing operations. A hole group formed by impact ionization is retained within the semiconductor base to have logic storage data that is at least three-valued.
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公开(公告)号：US20240179886A1
公开(公告)日：2024-05-30
申请号：US18517572
申请日：2023-11-22
发明人： Nozomu HARADA , Masakazu KAKUMU , Koji SAKUI
IPC分类号： H10B12/00 , G11C11/405 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/405 , G11C11/4096
摘要： In a memory cell including a first gate insulating layer 5 and a first gate conductor layer 6 surrounding a pillar-shaped P layer 3a standing on a P layer substrate 1, a second gate insulating layer 9 in contact with a P layer 3b in contact with an upper surface of the P layer 3a, and N+ layers 11a and 11b at both ends of the P layer 3b and a MOS transistor including a pillar-shaped P layer 3aa standing on a P layer substrate 1a connecting to the same P layer substrate 1, a third gate insulating layer 9a in contact with the P layer 3aa, a third gate conductor layer 10a, and N+ layers 11aa and 11ba at both ends of a P layer 3ba, bottom portions of the P layer 3b and the P layer 3ba are located at substantially the same position.
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公开(公告)号：US20230402089A1
公开(公告)日：2023-12-14
申请号：US18331328
申请日：2023-06-08
发明人： Masakazu KAKUMU , Koji Sakui , Nozomu Harada
IPC分类号： G11C11/4096 , H10B12/00 , H01L29/423
CPC分类号： G11C11/4096 , H10B12/20 , H01L29/42392
摘要： A dynamic flash memory includes a p layer as a semiconductor base material; first and second n+ layers extending on opposite sides thereof; a first gate insulating layer partially covering the p layer; a first gate conductor layer provided thereon; a second gate insulating layer provided in contact with the first gate insulating layer and partially covering the p layer; and a second gate conductor layer provided on the second gate insulating layer and electrically isolated from the first gate conductor layer. The first and second n+ layers, and the first and second gate conductor layers are respectively connected to a source line, a bit line, a word line, and a plate line. A voltage applied to each terminal during memory erasing is always greater than or equal to 0 V such that 2 V and 0.6 V are respectively applied to the plate line and the bit line.
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公开(公告)号：US20230317142A1
公开(公告)日：2023-10-05
申请号：US18194960
申请日：2023-04-03
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： G11C11/409 , H10B12/00
CPC分类号： G11C11/409 , H10B12/20
摘要： A p layer is a semiconductor base material. An n+ layer is disposed on one extension side. An n+ layer is disposed on the opposite side in contact with the p layer. A gate insulating layer partially covers the p layer. A first gate conductor layer contacts the insulating layer. A second gate conductor layer is electrically separated from the first gate conductor layer. Memory operation is performed by applying voltage to each of the layers. In the operation, the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area is larger than the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area.
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公开(公告)号：US20230145678A1
公开(公告)日：2023-05-11
申请号：US17981634
申请日：2022-11-07
发明人： Riichiro SHIROTA , Nozomu HARADA , Koji SAKUI , Masakazu KAKUMU
IPC分类号： G11C11/4097 , H01L27/108 , G11C11/408
CPC分类号： G11C11/4097 , H01L27/10802 , G11C11/4085
摘要： A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.
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公开(公告)号：US20230039991A1
公开(公告)日：2023-02-09
申请号：US17878485
申请日：2022-08-01
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H01L27/108 , H01L29/78 , G11C11/4096 , G11C5/06 , H01L29/06
摘要： An n+ layer 3a connected to a source line SL at both ends, an n+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.
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