公开(公告)号：US20210020694A1

公开(公告)日：2021-01-21

申请号：US16812354

申请日：2020-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  Hung-Yueh Chen ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L23/532 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528 ,  H01L43/02

Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.

公开(公告)号：US10355048B1

公开(公告)日：2019-07-16

申请号：US15920008

申请日：2018-03-13

Applicant: United Microelectronics Corp.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L21/76 ,  H01L29/78 ,  G11C11/16 ,  H01L29/06 ,  H01L21/762 ,  H01L43/12 ,  H01L43/02 ,  H01L21/3205 ,  H01F10/32 ,  H01L43/08

Abstract: An isolation structure is disposed between fin field effect transistors of a magnetic random access memory (MRAM) device. The isolation structure includes a fin line substrate, having a trench crossing the fin line substrate. An oxide layer is disposed on the fin line substrate other than the trench. A liner layer is disposed on an indent surface of the trench. A nitride layer is disposed on the liner layer, partially filling the trench. An oxide residue is disposed on the nitride layer within the trench at a bottom portion of the trench. A gate-like structure is disposed on the oxide layer and also fully filling the trench.

公开(公告)号：US12156478B2

公开(公告)日：2024-11-26

申请号：US18110337

申请日：2023-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

公开(公告)号：US11895926B2

公开(公告)日：2024-02-06

申请号：US17088531

申请日：2020-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

公开(公告)号：US11800723B2

公开(公告)日：2023-10-24

申请号：US17019340

申请日：2020-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Hung-Yueh Chen ,  Rai-Min Huang ,  Jia-Rong Wu ,  Yu-Ping Wang

IPC: G11C11/16 ,  H10B61/00 ,  G11C5/06 ,  G11C5/02 ,  H10N50/80

CPC classification number: H10B61/20 ,  G11C5/025 ,  G11C5/06 ,  G11C11/161 ,  H10N50/80

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, a first gate pattern and a second gate pattern extending along the second direction adjacent to one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction adjacent to another side of the first contact plug.

公开(公告)号：US20230292627A1

公开(公告)日：2023-09-14

申请号：US18200592

申请日：2023-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Ching-Hua Hsu ,  Hung-Yueh Chen

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：US11665973B2

公开(公告)日：2023-05-30

申请号：US17736069

申请日：2022-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H10N50/01

CPC classification number: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.

公开(公告)号：US11637233B2

公开(公告)日：2023-04-25

申请号：US17086447

申请日：2020-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Si-Han Tsai ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

公开(公告)号：US20220336735A1

公开(公告)日：2022-10-20

申请号：US17857185

申请日：2022-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

公开(公告)号：US11417838B2

公开(公告)日：2022-08-16

申请号：US16884060

申请日：2020-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.