公开(公告)号：US20200381431A1

公开(公告)日：2020-12-03

申请号：US16995941

申请日：2020-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US10784261B2

公开(公告)日：2020-09-22

申请号：US16697800

申请日：2019-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L27/14 ,  H01L27/146 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US09299624B2

公开(公告)日：2016-03-29

申请号：US14159657

申请日：2014-01-21

Applicant: United Microelectronics Corp.

Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

IPC: H01L21/66 ,  H01L25/07 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/1304 ,  H01L2924/1434 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/014

Abstract: A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.

Abstract translation: 提供一种叠层半导体结构及其制造方法。 提供了堆叠的半导体结构，其包括第一半导体衬底，第二半导体衬底，电介质层，沟槽，通孔和导电结构。 第一半导体衬底包括在第一衬底部分的有源表面上的第一衬底部分和第一导电层。 第二半导体衬底包括在第二衬底部分的有源表面上的第二衬底部分和第二导电层。 沟槽穿过第二衬底部分并暴露第二导电层。 通孔穿过介电层并暴露出第一导电层。 导电结构具有填充沟槽的上部和填充通孔的下部。 上部的相对侧面超过下部的相对侧面。

公开(公告)号：US20150323586A1

公开(公告)日：2015-11-12

申请号：US14803137

申请日：2015-07-20

Applicant: United Microelectronics Corp.

Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

IPC: G01R31/26 ,  H01L21/66

CPC classification number: G01R31/2642 ,  G06F17/50 ,  H01L22/14 ,  H01L22/20

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract translation: 为了改善晶片制造，通过确定晶片产量预测的屈服域的系数和晶片寿命预测的寿命域，整合域，电/布局域，计量/缺陷域和 机器传感器域以分层方式。 借助于层次确定的系数，可以减少预测中的噪声，从而可以提高晶片的产量或寿命的预测结果的精度。

公开(公告)号：US11916075B2

公开(公告)日：2024-02-27

申请号：US17741123

申请日：2022-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/823481 ,  H01L21/823892 ,  H01L29/7813

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US11119625B1

公开(公告)日：2021-09-14

申请号：US17099872

申请日：2020-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zheng-Yang Li ,  Chung-Jung Chen ,  Chun-Man Li ,  Li-Hsin Yang ,  Ching-Pei Lin ,  Ji-Fu Kung

IPC: G06F3/0481 ,  G06F3/0484

Abstract: A remote control device for a manufacturing equipment and a method for detecting manual control are provided. The method for detecting the manual control on the manufacturing equipment includes the following steps. A cursor pattern is created. When the user interface is automatically controlled, a history location of the cursor pattern shown on a user interface of the manufacturing equipment is detected to obtain a location distribution. The location distribution is stored. A current location of the cursor pattern shown on the user interface is detected. If the current location is not within the location distribution, it is deemed that the user interface is manually controlled.

公开(公告)号：US10570507B2

公开(公告)日：2020-02-25

申请号：US15950152

申请日：2018-04-10

Applicant: United Microelectronics Corp.

Inventor： Neng-Hsing Shen ,  Chien-Wen Yang ,  Chun-Man Li ,  Ji-Fu Kung ,  Ching-Pei Lin

IPC: G06F19/00 ,  C23C14/54 ,  C23C14/48 ,  H01L21/66 ,  G06K9/00 ,  G05B15/02 ,  H01L21/265

Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.

公开(公告)号：US10529715B2

公开(公告)日：2020-01-07

申请号：US15427512

申请日：2017-02-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L21/304 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US20190276930A1

公开(公告)日：2019-09-12

申请号：US15950152

申请日：2018-04-10

Applicant: United Microelectronics Corp.

Inventor： Neng-Hsing Shen ,  Chien-Wen Yang ,  Chun-Man Li ,  Ji-Fu Kung ,  Ching-Pei Lin

IPC: C23C14/54 ,  C23C14/48 ,  H01L21/66 ,  G05B15/02 ,  G06K9/00

Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.

公开(公告)号：US20150206810A1

公开(公告)日：2015-07-23

申请号：US14159657

申请日：2014-01-21

Applicant: United Microelectronics Corp.

Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

IPC: H01L21/66 ,  H01L25/00 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/1304 ,  H01L2924/1434 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/014

Abstract: A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.

Abstract translation: 提供一种叠层半导体结构及其制造方法。 提供了堆叠的半导体结构，其包括第一半导体衬底，第二半导体衬底，电介质层，沟槽，通孔和导电结构。 第一半导体衬底包括在第一衬底部分的有源表面上的第一衬底部分和第一导电层。 第二半导体衬底包括在第二衬底部分的有源表面上的第二衬底部分和第二导电层。 沟槽穿过第二衬底部分并暴露第二导电层。 通孔穿过介电层并暴露出第一导电层。 导电结构具有填充沟槽的上部和填充通孔的下部。 上部的相对侧面超过下部的相对侧面。