公开(公告)号：US20210288634A1

公开(公告)日：2021-09-16

申请号：US16847682

申请日：2020-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Yu-Lin Chen

IPC: H03K5/13

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

公开(公告)号：US10707305B2

公开(公告)日：2020-07-07

申请号：US16354126

申请日：2019-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US20190214463A1

公开(公告)日：2019-07-11

申请号：US16354126

申请日：2019-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7391 ,  H01L29/7848 ,  H01L29/785

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US20240290771A1

公开(公告)日：2024-08-29

申请号：US18657811

申请日：2024-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3≤D3−S, L4≤D4−S, and D3≠D4.

公开(公告)号：US11984442B2

公开(公告)日：2024-05-14

申请号：US17715974

申请日：2022-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

公开(公告)号：US20230097189A1

公开(公告)日：2023-03-30

申请号：US17868770

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: G06F30/392 ,  G06F30/30

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

公开(公告)号：US11368146B2

公开(公告)日：2022-06-21

申请号：US16847682

申请日：2020-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Yu-Lin Chen

IPC: H03K5/13 ,  H03K5/00

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

公开(公告)号：US09960083B1

公开(公告)日：2018-05-01

申请号：US15342114

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-You Chen ,  Cheng-Guo Chen ,  Kun-Yuan Wu ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo ,  Shang-Jr Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.