公开(公告)号：US20170207060A1

公开(公告)日：2017-07-20

申请号：US15001249

申请日：2016-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Chun Lin ,  Chih-Chieh Chou ,  Shih-Cheng Chen ,  Chung-Chih Hung ,  Yung-Teng Tsai ,  Chi-Hung Chan

IPC: H01J37/22 ,  H01L21/66 ,  H01J37/26

CPC classification number: H01L22/34 ,  H01J37/244 ,  H01J2237/24495 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/14 ,  H01L22/30

Abstract: A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.

公开(公告)号：US20240332189A1

公开(公告)日：2024-10-03

申请号：US18136885

申请日：2023-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Ko-Wei Lin ,  Ying-Wei Yen ,  Chun-Ling Lin ,  Po-Jen Chuang

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53266

Abstract: A method for fabricating an interconnect structure is disclosed. A substrate with a first dielectric layer is provided. A first conductor is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench is formed in the second dielectric layer to expose the top surface of the first conductor. An annealing process is performed on the top surface of the first conductor. The annealing process includes the conditions of a temperature of 400-450° C., duration less than 5 minutes, and gaseous atmosphere comprising hydrogen and nitrogen.

公开(公告)号：US20230369227A1

公开(公告)日：2023-11-16

申请号：US18226784

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US11756888B2

公开(公告)日：2023-09-12

申请号：US17493852

申请日：2021-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L27/02

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US20220028787A1

公开(公告)日：2022-01-27

申请号：US17493852

申请日：2021-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US20180083141A1

公开(公告)日：2018-03-22

申请号：US15823616

申请日：2017-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Tsai-Yu Wen ,  Shan Ye ,  Tsuo-Wen Lu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/78391 ,  H01L29/40111 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

公开(公告)号：US09711326B1

公开(公告)日：2017-07-18

申请号：US15001249

申请日：2016-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Chun Lin ,  Chih-Chieh Chou ,  Shih-Cheng Chen ,  Chung-Chih Hung ,  Yung-Teng Tsai ,  Chi-Hung Chan

IPC: H01J37/22 ,  H01J37/26 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01J37/244 ,  H01J2237/24495 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/14 ,  H01L22/30

Abstract: A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.