公开(公告)号：US12057401B2

公开(公告)日：2024-08-06

申请号：US18226784

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US20240363539A1

公开(公告)日：2024-10-31

申请号：US18764355

申请日：2024-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US11791413B2

公开(公告)日：2023-10-17

申请号：US17392222

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Shih-Cheng Chen ,  Chia-Wei Chang ,  Chia-Ming Kuo ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L23/10

CPC classification number: H01L29/7851 ,  H01L21/02126 ,  H01L23/10 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

公开(公告)号：US20230014253A1

公开(公告)日：2023-01-19

申请号：US17392222

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Shih-Cheng Chen ,  Chia-Wei Chang ,  Chia-Ming Kuo ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L23/10

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

公开(公告)号：US10204788B1

公开(公告)日：2019-02-12

申请号：US15859721

申请日：2018-01-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shan Ye ,  Shih-Cheng Chen ,  Tsuo-Wen Lu ,  Tzu-Hsiang Su ,  Po-Jen Chuang

IPC: H01L21/28 ,  H01L21/02 ,  C23C16/455 ,  H01L29/51

Abstract: A method of forming a high dielectric constant (high-k) dielectric layer by atomic layer deposition includes the following steps. Cycles are performed one after another, and each of the cycles sequentially includes performing a first oxygen precursor pulse to supply an oxygen precursor to a substrate disposed in a reactor; performing a first oxygen precursor purge after the first oxygen precursor pulse; performing a chemical precursor pulse to supply a chemical precursor to the substrate after the first oxygen precursor purge; and performing a chemical precursor purge after the chemical precursor pulse. The first oxygen precursor pulse, the first oxygen precursor purge, the chemical precursor pulse, and the chemical precursor purge are repeated by at least 3 cycles. A second oxygen precursor pulse is performed to supply an oxygen precursor to the substrate after the cycles. A second oxygen precursor purge is performed after the second oxygen precursor pulse.

公开(公告)号：US09871136B2

公开(公告)日：2018-01-16

申请号：US15206319

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Tsai-Yu Wen ,  Shan Ye ,  Tsuo-Wen Lu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

公开(公告)号：US09330902B1

公开(公告)日：2016-05-03

申请号：US14731227

申请日：2015-06-04

Applicant: United Microelectronics Corp.

Inventor： Tsai-Yu Wen ,  Shih-Cheng Chen ,  Shan Ye ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/3205 ,  H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7836

Abstract: A method for forming a HfOx film based on atomic layer deposition (ALD) process includes: providing a substrate; dividing a plurality of ALD cycles as needed into multiple depositing stages, wherein each of the ALD cycles includes applying HfCl4 pulse and applying H2O pulse over the substrate and a content ratio of HfCl4 to H2O is different and increasing for the depositing stages; and performing the depositing stages to form a HfOx film.

Abstract translation: 基于原子层沉积（ALD）工艺形成HfO x膜的方法包括：提供衬底; 根据需要将多个ALD循环分成多个沉积阶段，其中每个ALD循环包括施加HfCl 4脉冲并在衬底上施加H 2 O脉冲，并且HfCl 4与H 2 O的含量比不同并且对于沉积阶段而言增加; 并进行沉积阶段以形成HfO x膜。

公开(公告)号：US11171091B2

公开(公告)日：2021-11-09

申请号：US16695028

申请日：2019-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

公开(公告)号：US20210125927A1

公开(公告)日：2021-04-29

申请号：US16695028

申请日：2019-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

公开(公告)号：US20170358684A1

公开(公告)日：2017-12-14

申请号：US15206319

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Tsai-Yu Wen ,  Shan Ye ,  Tsuo-Wen Lu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.