公开(公告)号：US20190287976A1

公开(公告)日：2019-09-19

申请号：US15959291

申请日：2018-04-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Po-Chun Chen ,  Chia-Lung Chang

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/02

Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.

公开(公告)号：US20190148382A1

公开(公告)日：2019-05-16

申请号：US15810145

申请日：2017-11-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Han-Yung Tsai ,  Tzu-Chin Wu

IPC: H01L27/108 ,  H01L21/285

CPC classification number: H01L27/10852 ,  H01L21/28556 ,  H01L27/10814 ,  H01L27/10823

Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.

公开(公告)号：US10262895B2

公开(公告)日：2019-04-16

申请号：US15859766

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/108 ,  H01L21/8234 ,  H01L49/02

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

公开(公告)号：US09343573B2

公开(公告)日：2016-05-17

申请号：US14557469

申请日：2014-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.

Abstract translation: 一种制造具有不均匀应力层的晶体管器件的方法，包括以下过程。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层的拉伸应力低于第二拉伸应力层的拉伸应力。

公开(公告)号：US12040234B2

公开(公告)日：2024-07-16

申请号：US17393387

申请日：2021-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US10468417B2

公开(公告)日：2019-11-05

申请号：US15959291

申请日：2018-04-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Po-Chun Chen ,  Chia-Lung Chang

IPC: H01L23/48 ,  H01L27/108 ,  H01L21/02 ,  H01L21/8234

Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.

公开(公告)号：US10249706B1

公开(公告)日：2019-04-02

申请号：US15951185

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Lung Chang ,  Wei-Hsin Liu ,  Po-Chun Chen ,  Yi-Wei Chen ,  Han-Yung Tsai ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L49/02 ,  H01L27/108

Abstract: The present invention provides a semiconductor structure comprising a substrate, a cell region defined on the substrate, a plurality of lower electrodes of the capacitor structures located in the cell region, an top support structure, contacting a top region of the lower electrode structure, and at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other.

公开(公告)号：US20180190658A1

公开(公告)日：2018-07-05

申请号：US15859766

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76834 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02348 ,  H01L21/76825 ,  H01L21/823475 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

公开(公告)号：US09219151B1

公开(公告)日：2015-12-22

申请号：US14477214

申请日：2014-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Tzu-Chin Wu

IPC: H01L21/31 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/3105 ,  H01L29/7833

Abstract: A method for manufacturing a silicon nitride layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for manufacturing a silicon nitride layer includes forming the silicon nitride layer and stressing the silicon nitride layer by a high density plasma chemical vapor deposition (HDPCVD) treatment.

Abstract translation: 提供了一种制造氮化硅层的方法及其制造应用该氮化硅层的半导体结构的方法。 制造氮化硅层的方法包括形成氮化硅层并通过高密度等离子体化学气相沉积（HDPCVD）处理来压制氮化硅层。

公开(公告)号：US20150206803A1

公开(公告)日：2015-07-23

申请号：US14158857

申请日：2014-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Tzu-Chin Wu ,  Jei-Ming Chen ,  Yu-Ren Wang ,  Chun-Yuan Wu ,  Chin-Fu Lin

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/823462 ,  H01L21/31116 ,  H01L21/76837 ,  H01L21/823475

Abstract: A method of forming an inter-level dielectric layer including the following step is provided. Two gate structures are formed on a substrate. A first oxide layer is formed to conformally cover the two gate structures and the substrate. The first oxide layer is etched ex-situ by a high density plasma (HDP) etching process. A second oxide layer is formed in-situ on the first oxide layer and fills a gap between the two gate structures by a high density plasma (HDP) depositing process.

Abstract translation: 提供一种形成包括以下步骤的层间电介质层的方法。 在基板上形成两个栅极结构。 形成第一氧化物层以保形地覆盖两个栅极结构和衬底。 通过高密度等离子体（HDP）蚀刻工艺非原位蚀刻第一氧化物层。 在第一氧化物层上原地形成第二氧化物层，并通过高密度等离子体（HDP）沉积工艺填充两个栅极结构之间的间隙。