公开(公告)号：US11024672B2

公开(公告)日：2021-06-01

申请号：US16418770

申请日：2019-05-21

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.

公开(公告)号：US20200328255A1

公开(公告)日：2020-10-15

申请号：US16418770

申请日：2019-05-21

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.

公开(公告)号：US09923028B1

公开(公告)日：2018-03-20

申请号：US15402630

申请日：2017-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H05K999/99

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

公开(公告)号：US20170062279A1

公开(公告)日：2017-03-02

申请号：US14835700

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sih-Yun Wei ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/6659

Abstract: A transistor set forming process includes the following steps. A substrate having a first area and a second area is provided. An implantation process is performed to form a diffusion region of a first transistor in the substrate of the first area and a channel region of a second transistor in the substrate of the second area at the same time.

Abstract translation: 晶体管组形成工艺包括以下步骤。 提供具有第一区域和第二区域的衬底。 执行注入工艺，以在第一区域的衬底中的第一晶体管的扩散区域和第二区域的衬底中的第二晶体管的沟道区域同时形成。

公开(公告)号：US20230033836A1

公开(公告)日：2023-02-02

申请号：US17960789

申请日：2022-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

公开(公告)号：US11508783B2

公开(公告)日：2022-11-22

申请号：US17235785

申请日：2021-04-20

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.

公开(公告)号：US20200083344A1

公开(公告)日：2020-03-12

申请号：US16123868

申请日：2018-09-06

Applicant: United Microelectronics Corp.

Inventor： Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chuan-Fu Wang ,  Yu-Huang Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/49 ,  H01L29/45

Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

公开(公告)号：US20180175110A1

公开(公告)日：2018-06-21

申请号：US15884827

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H05K999/99

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

公开(公告)号：US12082405B2

公开(公告)日：2024-09-03

申请号：US18203054

申请日：2023-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7881

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

公开(公告)号：US11832444B2

公开(公告)日：2023-11-28

申请号：US17960789

申请日：2022-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H01L29/423 ,  H01L29/66 ,  H10B41/30 ,  H01L29/78 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7881

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).