公开(公告)号：US20150067301A1

公开(公告)日：2015-03-05

申请号：US14526029

申请日：2014-10-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F15/82 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

Abstract translation: 微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。 微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。 作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。 微处理器还包括耦合到硬件指令转换器的执行流水线。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。 响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

公开(公告)号：US20160239303A1

公开(公告)日：2016-08-18

申请号：US15140010

申请日：2016-04-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30178 ,  G06F9/26 ,  G06F9/268 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/3802

Abstract: A microprocessor includes compressed and uncompressed microcode memory storages, having N-bit wide and M-bit wide addressable words, respectively, where N

Abstract translation: 微处理器包括压缩和未压缩的微代码存储器存储器，其中N

公开(公告)号：US20160202980A1

公开(公告)日：2016-07-14

申请号：US14963134

申请日：2015-12-08

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3016 ,  G06F9/30025 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/4401 ,  G06F12/0875 ,  G06F2212/452

Abstract: A microprocessor natively translates and executes instructions of both the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA. An instruction formatter extracts distinct ARM instruction bytes from a stream of instruction bytes received from an instruction cache and formats them. ARM and x86 instruction length decoders decode ARM and x86 instruction bytes, respectively, and determine instruction lengths of ARM and x86 instructions. An instruction translator translates the formatted x86 ISA and ARM ISA instructions into microinstructions of a unified microinstruction set architecture of the microprocessor. An execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.

Abstract translation: 微处理器本地翻译和执行x86指令集架构（ISA）和高级RISC机器（ARM）ISA的指令。 指令格式化器从指令高速缓存接收的指令字节流中提取不同的ARM指令字节，并对其进行格式化。 ARM和x86指令长度解码器分别解码ARM和x86指令字节，并确定ARM和x86指令的指令长度。 指令翻译器将格式化的x86 ISA和ARM ISA指令转换为微处理器的统一微指令集架构的微指令。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。

公开(公告)号：US20160104009A1

公开(公告)日：2016-04-14

申请号：US14884502

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN ,  THOMAS A. CRISPIN

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/74 ,  G06F9/30

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor and method are provided for securely decrypting and executing encrypted instructions within a microprocessor. A plurality of master keys are stored in a secure memory. Encrypted instructions are fetched from an instruction cache. A set of one or more master keys are selected from the secure memory based upon an encrypted instruction fetch address. The selected set of master keys or a decryption key derived therefrom is used to decrypt the encrypted instructions fetched from the instruction cache. The decrypted instructions are then securely executed within the microprocessor. In one implementation, the master keys are intervolved with each other to produce a new decryption key with every fetch quantum. Moreover, a new set of master keys is selected with every new block of instructions.

Abstract translation: 提供了微处理器和方法，用于在微处理器内安全解密和执行加密指令。 多个主密钥存储在安全存储器中。 从指令缓存中提取加密指令。 基于加密的指令提取地址从安全存储器中选择一组或多个主密钥。 所选择的一组主密钥或从其导出的解密密钥用于解密从指令高速缓存取出的加密指令。 然后在微处理器内安全地执行解密的指令。 在一个实现中，主密钥彼此相互交织以产生具有每个获取量子的新的解密密钥。 此外，每个新的指令块都选择一组新的主键。

公开(公告)号：US20150227407A1

公开(公告)日：2015-08-13

申请号：US14522530

申请日：2014-10-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F1/3215 ,  G06F1/3221 ,  G06F1/3243 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3863 ,  G06F11/0721 ,  G06F17/10 ,  Y02D10/152 ,  Y02D10/154

Abstract: A processor includes an indicator configured to indicate a first mode or a second mode and a functional unit configured to perform computations with a full degree of accuracy when the indicator indicates the first mode and to perform computations with less than the full degree of accuracy when the indicator indicates the second mode.

Abstract translation: 处理器包括被配置为指示第一模式或第二模式的指示符和功能单元，其被配置为当指示符指示第一模式时以完全准确的程度执行计算，并且当所述指示符指示第一模式时，执行小于全部准确度的计算 指示灯指示第二种模式。