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公开(公告)号：US20160098277A1
公开(公告)日：2016-04-07
申请号：US14569313
申请日：2014-12-12
Applicant: VIA TECHNOLOGIES, INC.
Inventor： MATTHEW DANIEL DAY , G. GLENN HENRY , TERRY PARKS
IPC: G06F9/38
CPC classification number: G06F9/3814 , G06F9/38 , G06F9/3836
Abstract: A compressing instruction queue for a microprocessor including a queue and redirect logic. The queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the queue without leaving unused storage locations and beginning at a first available storage location in the queue. The redirect logic performs redirection and compression to eliminate empty locations or holes in the queue and to reduce the number of write ports interfaced with each storage location of the queue.
Abstract translation: 用于微处理器的压缩指令队列，包括队列和重定向逻辑。 队列包括存储位置矩阵，包括N行和M列，用于按顺序存储微处理器的微指令。 重定向逻辑被配置为每个周期的时钟信号接收和写入多个微指令到队列的顺序存储位置，而不留下未使用的存储位置并且从队列中的第一可用存储位置开始。 重定向逻辑执行重定向和压缩以消除队列中的空位置或空洞，并减少与队列的每个存储位置接口的写入端口的数量。
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公开(公告)号：US20150227372A1
公开(公告)日：2015-08-13
申请号：US14522512
申请日：2014-10-23
Applicant: VIA TECHNOLOGIES, INC.
Inventor： G. GLENN HENRY , TERRY PARKS , RODNEY E. HOOKER
CPC classification number: G06F9/30145 , G06F9/30014 , G06F9/30076 , G06F9/30185 , G06F9/30189 , G06F11/0721 , G06F11/0793
Abstract: A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.
Abstract translation: 一种处理器包括一个译码器，该解码器解码指示处理器以近似方式执行后续计算的指令，以及响应该指令以近似方式执行后续计算的功能单元。 指令指示处理器清除与存储在处理器的通用寄存器中的值相关联的错误量。 错误量表示与处理器以近似的方式执行的计算结果相关联的错误量。 处理器还会根据指令清除错误量。 另一个指令指定要执行的计算，并且包括指示处理器以近似的方式执行计算的前缀。 功能单元以由前缀指定的近似方式执行由指令指定的计算。
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公开(公告)号：US20160105282A1
公开(公告)日：2016-04-14
申请号：US14884416
申请日：2015-10-15
Applicant: VIA TECHNOLOGIES, INC.
Inventor： G. GLENN HENRY , TERRY PARKS , BRENT BEAN , THOMAS A. CRISPIN
CPC classification number: H04L9/0825 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0855 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/6026 , G06F2221/2107 , H04L9/0618 , H04L9/0827 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
Abstract: A secure memory, key expansion logic, and decryption logic are provided for a microprocessor that executes encrypted instructions. The secure memory stores a plurality of decryption key primitives. The key expansion logic selects two or more decryption key primitives from the secure memory and then derives a decryption key from them. The decryption logic uses the decryption key to decrypt an encrypted instruction fetched from the instruction cache. The decryption key primitives are selected on the basis of an encrypted instruction address, one of them is rotated by an amount also determined by the encrypted instruction address, and then they are additively or subtractively accumulated, also on the basis of the encrypted instruction address.
Abstract translation: 为执行加密指令的微处理器提供安全存储器，密钥扩展逻辑和解密逻辑。 安全存储器存储多个解密密钥基元。 密钥扩展逻辑从安全存储器中选择两个或多个解密密钥原语，然后从其中导出解密密钥。 解密逻辑使用解密密钥来解密从指令高速缓存取出的加密指令。 解密密钥基元是根据加密指令地址进行选择的，其中一个被转换了由加密指令地址确定的量，然后也根据加密指令地址进行加法或减法累加。
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4.发明申请公开(公告)号：US20160104010A1
公开(公告)日：2016-04-14
申请号：US14884525
申请日：2015-10-15
Applicant: VIA TECHNOLOGIES, INC.
Inventor： G. GLENN HENRY , TERRY PARKS , BRENT BEAN , THOMAS A. CRISPIN
CPC classification number: G06F21/72 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/74 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0827 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
Abstract: A microprocessor conditionally grants a request to switch from a normal execution mode in which encrypted instructions cannot be executed, into a secure execution mode (SEM). Thereafter, the microprocessor executes a plurality of instructions, including a store-key instruction to write a set of one or more cryptographic key values into a secure memory of the microprocessor. After fetching an encrypted program from an instruction cache, the microprocessor decrypts the encrypted program into plaintext instructions using decryption logic within the microprocessor's instruction-processing pipeline.
Abstract translation: 微处理器有条件地授予从加密指令不能被执行的正常执行模式切换到安全执行模式（SEM）的请求。 此后，微处理器执行多个指令，包括将一组一个或多个加密密钥值写入微处理器的安全存储器的存储键指令。 在从指令高速缓存获取加密程序之后，微处理器使用微处理器指令处理流水线内的解密逻辑将加密程序解密为明文指令。
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公开(公告)号：US20180032341A1
公开(公告)日：2018-02-01
申请号：US15728551
申请日：2017-10-10
Applicant: VIA TECHNOLOGIES, INC.
Inventor： G. GLENN HENRY , TERRY PARKS
CPC classification number: G06F9/30145 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3836 , G06F9/3859
Abstract: A microprocessor performs an If-Then (IT) instruction and an associated IT block by extracting condition information from the IT instruction and for each instruction of the IT block: determining a respective condition for the instruction using the extract condition information, translating the instruction into a microinstruction, and conditionally executing the microinstruction based on the respective condition. For a first instruction, the translating comprises fusing the IT instruction with the first IT block instruction. A hardware instruction translation unit performs the extracting, determining and translating. Execution units conditionally execute the microinstructions. The hardware instruction translation unit and execution units are distinct hardware elements and are coupled together. The hardware translation unit performs the extracting, fusing and for each instruction of the IT block the determining and translating without writing intermediate results to a system memory, without execution of other architectural instructions by the microprocessor, and/or in six clock cycles or less.
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Patent Agency Ranking
公开(公告)号：US20170003707A1
公开(公告)日：2017-01-05
申请号：US15265127
申请日：2016-09-14
Applicant: VIA TECHNOLOGIES, INC.
Inventor： G. GLENN HENRY , TERRY PARKS , BRENT BEAN , STEPHAN GASKINS
CPC classification number: G06F9/3885 , G06F1/04 , G06F1/12 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/30032 , G06F9/30047 , G06F9/30079 , G06F9/30087 , G06F9/30105 , G06F9/30145 , G06F9/3802 , G06F9/3861 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F9/4418 , G06F12/0808 , G06F12/084 , G06F12/0875 , G06F13/24 , G06F13/364 , G06F13/42 , G06F21/53 , G06F21/57 , G06F2212/452 , G06F2212/6028 , G06F2212/62 , H01L22/34 , H04L9/0877 , H04L9/0897 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/30 , Y02D10/10 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/171 , Y02D10/172 , Y02D10/30 , Y02D50/20
Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.
Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。
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7.发明申请ASYMMETRIC PROCESSOR WITH CORES THAT SUPPORT DIFFERENT ISA INSTRUCTION SUBSETS 审中-公开不相称的处理器，支持不同的ISA指令服务公开(公告)号：US20160162293A1
公开(公告)日：2016-06-09
申请号：US14956541
申请日：2015-12-02
Applicant: VIA TECHNOLOGIES, INC.
Inventor： RODNEY E. HOOKER , TERRY PARKS , G. GLENN HENRY
IPC: G06F9/30
CPC classification number: G06F9/3009 , G06F1/3206 , G06F1/3293 , G06F9/5044 , Y02D10/122
Abstract: An asymmetric multi-core processor uses at least two asymmetric cores to collectively support the instructions of an instruction set architecture (ISA). A general-feature core and a special feature core that support different instruction subsets of the ISA. A switch manager detects whether a thread includes an instruction that is not supported by the currently-executing core and, after detecting such an instruction, switches the thread to the other core.
Abstract translation: 非对称多核处理器使用至少两个不对称核来共同支持指令集架构（ISA）的指令。 通用功能核心和支持ISA不同指令子集的特殊功能核心。 交换机管理器检测线程是否包括当前执行的核心不支持的指令，并且在检测到这样的指令之后，将线程切换到另一个核心。
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公开(公告)号：US20160104011A1
公开(公告)日：2016-04-14
申请号：US14884547
申请日：2015-10-15
Applicant: VIA TECHNOLOGIES, INC.
Inventor： G. GLENN HENRY , TERRY PARKS , BRENT BEAN , THOMAS A. CRISPIN
CPC classification number: G06F21/72 , G06F9/30003 , G06F9/30079 , G06F9/3017 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/74 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0827 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
Abstract: A microprocessor is provided in which an encrypted program can replace the decryption keys that are used to decrypt sections of the encrypted program. The microprocessor may be decrypting and executing a first section of the encrypted program when it encounters, decrypts, and executes an encrypted store-key instruction to store a new set of decryption keys. After executing the store-key instruction, the microprocessor decrypts and executes a subsequent section of the encrypted program using the new set of decryption keys. On-the-fly key switching may occur numerous times with successive encrypted store-key instructions and successive sets of encrypted instructions.
Abstract translation: 提供了一种微处理器，其中加密程序可以替换用于解密加密程序的部分的解密密钥。 当加密程序遇到，解密和执行加密存储密钥指令以存储一组新的解密密钥时，微处理器可以解密并执行加密程序的第一部分。 在执行存储密钥指令之后，微处理器使用新的解密密钥解密并执行加密程序的后续部分。 随机密钥交换可能会随着连续的加密存储密钥指令和连续的加密指令集而发生多次。
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公开(公告)号：US20150227429A1
公开(公告)日：2015-08-13
申请号：US14522520
申请日：2014-10-23
Applicant: VIA TECHNOLOGIES, INC.
Inventor： G. GLENN HENRY , TERRY PARKS , RODNEY E. HOOKER
IPC: G06F11/14
CPC classification number: G06F11/1446 , G06F9/30014 , G06F9/30185 , G06F9/38 , G06F9/3863 , G06F11/0754 , G06F11/0793 , G06F11/1402 , G06F11/1435 , G06F2201/84
Abstract: A processor includes a storage configured to receive a snapshot of a state of the processor prior to performing a set of computations in an approximating manner. The processor also includes an indicator that indicates an amount of error accumulated while the set of computations is performed in the approximating manner. When the processor detects that the amount of error accumulated has exceeded an error bound, the processor is configured to restore the state of the processor to the snapshot from the storage.
Abstract translation: 处理器包括被配置为在以近似方式执行一组计算之前接收处理器状态的快照的存储器。 处理器还包括指示器，其指示在以近似方式执行计算集合时累积的误差量。 当处理器检测到累积的错误量超过了错误限制时，处理器被配置为将处理器的状态从存储恢复到快照。
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公开(公告)号：US20160162017A1
公开(公告)日：2016-06-09
申请号：US14994544
申请日：2016-01-13
Applicant: VIA TECHNOLOGIES, INC.
Inventor： G. GLENN HENRY , TERRY PARKS
CPC classification number: G06F1/3287 , G06F1/04 , G06F1/32 , G06F9/522 , G06F12/0891 , G06F2212/1028 , G06F2212/60
Abstract: A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core's target operating state.
Abstract translation: 多核微处理器支持向微处理器及其核心提供不同级别的性能和功耗的多个操作状态。 控制单元在所选择的时间将选定的磁芯置于选定的运行状态。 为核心外部的每个核心提供核心特定同步寄存器，并由控制单元读取。 每个核心通过将标识目标操作状态的值写入同步寄存器来响应指令以对准操作状态的指令。 如果行为不降低任何核心共享低于核心目标操作状态的资源的核心，控制单元就会产生影响共享资源的省电动作。
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