公开(公告)号：US20150067301A1

公开(公告)日：2015-03-05

申请号：US14526029

申请日：2014-10-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F15/82 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

Abstract translation: 微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。 微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。 作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。 微处理器还包括耦合到硬件指令转换器的执行流水线。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。 响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

公开(公告)号：US20150341218A1

公开(公告)日：2015-11-26

申请号：US14474623

申请日：2014-09-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： WEN-CHI CHEN ,  RODNEY E. HOOKER

IPC: H04L12/24

CPC classification number: H04L41/0833 ,  G06F15/177 ,  H04L41/0806

Abstract: A server includes a first module that receives information from a plurality of systems. Each system of the plurality of systems includes functional units that are dynamically configurable during operation of the system. The information from each system of the plurality of systems includes performance data collected while executing a program when the functional units are configured according to a configuration setting respective to the system. The server also includes a second module that analyzes the received information to select a best-performing configuration setting of the configuration settings received from the plurality of systems. The server also includes a third module that provides a new configuration setting to the plurality of systems. The new configuration setting is a modification of the best-performing configuration. The server iterates on receiving the information from the plurality of systems, analyzing the received information and providing the new configuration setting to the plurality of systems.

Abstract translation: 服务器包括从多个系统接收信息的第一模块。 多个系统中的每个系统包括在系统操作期间可动态配置的功能单元。 当根据与系统相对应的配置设置来配置功能单元时，来自多个系统的每个系统的信息包括在执行程序时收集的演奏数据。 服务器还包括第二模块，其分析所接收的信息以选择从多个系统接收的配置设置的最佳性能的配置设置。 服务器还包括向多个系统提供新的配置设置的第三模块。 新配置设置是对性能最佳的配置的修改。 服务器迭代接收来自多个系统的信息，分析所接收的信息并向多个系统提供新的配置设置。

公开(公告)号：US20160202980A1

公开(公告)日：2016-07-14

申请号：US14963134

申请日：2015-12-08

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3016 ,  G06F9/30025 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/4401 ,  G06F12/0875 ,  G06F2212/452

Abstract: A microprocessor natively translates and executes instructions of both the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA. An instruction formatter extracts distinct ARM instruction bytes from a stream of instruction bytes received from an instruction cache and formats them. ARM and x86 instruction length decoders decode ARM and x86 instruction bytes, respectively, and determine instruction lengths of ARM and x86 instructions. An instruction translator translates the formatted x86 ISA and ARM ISA instructions into microinstructions of a unified microinstruction set architecture of the microprocessor. An execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.

Abstract translation: 微处理器本地翻译和执行x86指令集架构（ISA）和高级RISC机器（ARM）ISA的指令。 指令格式化器从指令高速缓存接收的指令字节流中提取不同的ARM指令字节，并对其进行格式化。 ARM和x86指令长度解码器分别解码ARM和x86指令字节，并确定ARM和x86指令的指令长度。 指令翻译器将格式化的x86 ISA和ARM ISA指令转换为微处理器的统一微指令集架构的微指令。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。

公开(公告)号：US20160110289A1

公开(公告)日：2016-04-21

申请号：US14624981

申请日：2015-02-18

Applicant: VIA TECHNOLOGIES, INC.

Inventor： RODNEY E. HOOKER ,  ALBERT J. LOPER ,  JOHN MICHAEL GREER ,  MEERA RAMANI-AUGUSTIN

IPC: G06F12/08 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F9/30047 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/30109 ,  G06F9/3802 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/6022 ,  G06F2212/6024

Abstract: A hardware data prefetcher is comprised in a memory access agent, wherein the memory access agent is one of a plurality of memory access agents that share a memory. The hardware data prefetcher includes a prefetch trait that is initially either exclusive or shared. The hardware data prefetcher also includes a prefetch module that performs hardware prefetches from a memory block of the shared memory using the prefetch trait. The hardware data prefetcher also includes an update module that performs analysis of accesses to the memory block by the plurality of memory access agents and, based on the analysis, dynamically updates the prefetch trait to either exclusive or shared while the prefetch module performs hardware prefetches from the memory block using the prefetch trait.

Abstract translation: 硬件数据预取器包括在存储器访问代理中，其中存储器访问代理是共享存储器的多个存储器访问代理之一。 硬件数据预取器包括最初是独占的或共享的预取特征。 硬件数据预取器还包括预取模块，其使用预取特征从共享存储器的存储器块执行硬件预取。 硬件数据预取器还包括更新模块，其执行由多个存储器访问代理对存储块的访问的分析，并且基于该分析，在预取模块执行硬件预取从 内存块使用预取特征。

公开(公告)号：US20150227407A1

公开(公告)日：2015-08-13

申请号：US14522530

申请日：2014-10-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F1/3215 ,  G06F1/3221 ,  G06F1/3243 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3863 ,  G06F11/0721 ,  G06F17/10 ,  Y02D10/152 ,  Y02D10/154

Abstract: A processor includes an indicator configured to indicate a first mode or a second mode and a functional unit configured to perform computations with a full degree of accuracy when the indicator indicates the first mode and to perform computations with less than the full degree of accuracy when the indicator indicates the second mode.

Abstract translation: 处理器包括被配置为指示第一模式或第二模式的指示符和功能单元，其被配置为当指示符指示第一模式时以完全准确的程度执行计算，并且当所述指示符指示第一模式时，执行小于全部准确度的计算 指示灯指示第二种模式。

公开(公告)号：US20160162293A1

公开(公告)日：2016-06-09

申请号：US14956541

申请日：2015-12-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： RODNEY E. HOOKER ,  TERRY PARKS ,  G. GLENN HENRY

IPC: G06F9/30

CPC classification number: G06F9/3009 ,  G06F1/3206 ,  G06F1/3293 ,  G06F9/5044 ,  Y02D10/122

Abstract: An asymmetric multi-core processor uses at least two asymmetric cores to collectively support the instructions of an instruction set architecture (ISA). A general-feature core and a special feature core that support different instruction subsets of the ISA. A switch manager detects whether a thread includes an instruction that is not supported by the currently-executing core and, after detecting such an instruction, switches the thread to the other core.

Abstract translation: 非对称多核处理器使用至少两个不对称核来共同支持指令集架构（ISA）的指令。 通用功能核心和支持ISA不同指令子集的特殊功能核心。 交换机管理器检测线程是否包括当前执行的核心不支持的指令，并且在检测到这样的指令之后，将线程切换到另一个核心。

公开(公告)号：US20160110194A1

公开(公告)日：2016-04-21

申请号：US14625124

申请日：2015-02-18

Applicant: VIA TECHNOLOGIES, INC.

Inventor： RODNEY E. HOOKER ,  ALBERT J. LOPER ,  JOHN MICHAEL GREER

IPC: G06F9/30 ,  G06F12/02 ,  G06F12/08

CPC classification number: G06F9/30047 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/30109 ,  G06F9/3802 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/6022 ,  G06F2212/6024

Abstract: A processor includes a processing core that detects a predetermined program is running on the processor and looks up a prefetch trait associated with the predetermined program running on the processor, wherein the prefetch trait is either exclusive or shared. The processor also includes a hardware data prefetcher that performs hardware prefetches for the predetermined program using the prefetch trait. Alternatively, the processing core loads each of one or more range registers of the processor with a respective address range in response to detecting that the predetermined program is running on the processor. Each of the one or more address ranges has an associated prefetch trait, wherein the prefetch trait is either exclusive or shared. The hardware data prefetcher performs hardware prefetches for the predetermined program using the prefetch traits associated with the address ranges loaded into the range registers.

Abstract translation: 处理器包括检测在处理器上运行的预定程序的处理核心，并且查找与在处理器上运行的预定程序相关联的预取特征，其中预取特征是独占的或共享的。 处理器还包括硬件数据预取器，其使用预取特征对预定程序执行硬件预取。 或者，响应于检测到预定程序在处理器上运行，处理核心将具有相应地址范围的处理器的一个或多个范围寄存器中的每一个加载。 一个或多个地址范围中的每一个具有相关联的预取特征，其中预取特征是独占的或共享的。 硬件数据预取器使用与加载到范围寄存器中的地址范围相关联的预取特征来执行预定程序的硬件预取。

公开(公告)号：US20150227429A1

公开(公告)日：2015-08-13

申请号：US14522520

申请日：2014-10-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F11/14

CPC classification number: G06F11/1446 ,  G06F9/30014 ,  G06F9/30185 ,  G06F9/38 ,  G06F9/3863 ,  G06F11/0754 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/1435 ,  G06F2201/84

Abstract: A processor includes a storage configured to receive a snapshot of a state of the processor prior to performing a set of computations in an approximating manner. The processor also includes an indicator that indicates an amount of error accumulated while the set of computations is performed in the approximating manner. When the processor detects that the amount of error accumulated has exceeded an error bound, the processor is configured to restore the state of the processor to the snapshot from the storage.

Abstract translation: 处理器包括被配置为在以近似方式执行一组计算之前接收处理器状态的快照的存储器。 处理器还包括指示器，其指示在以近似方式执行计算集合时累积的误差量。 当处理器检测到累积的错误量超过了错误限制时，处理器被配置为将处理器的状态从存储恢复到快照。

公开(公告)号：US20150339132A1

公开(公告)日：2015-11-26

申请号：US14474699

申请日：2014-09-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： WEN-CHI CHEN ,  RODNEY E. HOOKER

IPC: G06F9/445 ,  G06F9/44

CPC classification number: G06F9/44505 ,  G06F9/448 ,  G06F15/177

Abstract: A system includes functional units that are dynamically configurable during operation of the system. The system also includes a first module that collects performance data while the system executes a program with the functional units configured according to a configuration setting. The system also includes a second module that sends information to a server. The information includes the performance data, the configuration setting and data from which the program may be identified. The system also includes a third module that instructs the system to re-configure the functional units with a new configuration setting received from the server while the program is being executed by the system. The new configuration setting is based on analysis by the server of the information sent by the system and of similar information sent by other systems that include the dynamically configurable functional units.

Abstract translation: 系统包括在系统运行期间可动态配置的功能单元。 系统还包括在系统执行程序时收集性能数据的第一模块，功能单元根据配置设置配置。 该系统还包括向服务器发送信息的第二个模块。 该信息包括性能数据，配置设置和可以识别程序的数据。 该系统还包括第三模块，其指示系统在系统执行程序时从服务器接收到的新配置设置来重新配置功能单元。 新的配置设置是基于服务器分析系统发送的信息以及其他系统发送的类似信息，包括动态配置的功能单元。

公开(公告)号：US20150309936A1

公开(公告)日：2015-10-29

申请号：US14790467

申请日：2015-07-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： RODNEY E. HOOKER

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/6022 ,  G06F2212/6028 ,  G06F2212/684 ,  G06F2212/654

Abstract: A microprocessor includes a translation lookaside buffer and a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer. The requested page table entry is included in a page table. The page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry. The microprocessor also includes hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table, and a second request to prefetch the second cache line into the microprocessor. The second request is selectively generated based at least on the determination made by the hardware logic.

Abstract translation: 微处理器包括翻译后备缓冲器和响应于翻译后备缓冲器中的虚拟地址的缺失而将微处理器加载到页表条目的第一请求。 请求的页表项包含在页表中。 该页表包含多条高速缓存行，包括包含所请求的页表项的第一高速缓存行。 微处理器还包括硬件逻辑，其确定与第一高速缓存行物理连续的第二高速缓存线是否在页表之外，以及将第二高速缓存线预取到微处理器中的第二请求。 至少基于硬件逻辑的判定来选择性地生成第二请求。