公开(公告)号：US20170003707A1

公开(公告)日：2017-01-05

申请号：US15265127

申请日：2016-09-14

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN ,  STEPHAN GASKINS

IPC: G06F1/12 ,  G06F1/32 ,  G06F9/44

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。

公开(公告)号：US20160104011A1

公开(公告)日：2016-04-14

申请号：US14884547

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN ,  THOMAS A. CRISPIN

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/74 ,  G06F9/30

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0827 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor is provided in which an encrypted program can replace the decryption keys that are used to decrypt sections of the encrypted program. The microprocessor may be decrypting and executing a first section of the encrypted program when it encounters, decrypts, and executes an encrypted store-key instruction to store a new set of decryption keys. After executing the store-key instruction, the microprocessor decrypts and executes a subsequent section of the encrypted program using the new set of decryption keys. On-the-fly key switching may occur numerous times with successive encrypted store-key instructions and successive sets of encrypted instructions.

Abstract translation: 提供了一种微处理器，其中加密程序可以替换用于解密加密程序的部分的解密密钥。 当加密程序遇到，解密和执行加密存储密钥指令以存储一组新的解密密钥时，微处理器可以解密并执行加密程序的第一部分。 在执行存储密钥指令之后，微处理器使用新的解密密钥解密并执行加密程序的后续部分。 随机密钥交换可能会随着连续的加密存储密钥指令和连续的加密指令集而发生多次。

公开(公告)号：US20160239303A1

公开(公告)日：2016-08-18

申请号：US15140010

申请日：2016-04-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30178 ,  G06F9/26 ,  G06F9/268 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/3802

Abstract: A microprocessor includes compressed and uncompressed microcode memory storages, having N-bit wide and M-bit wide addressable words, respectively, where N

Abstract translation: 微处理器包括压缩和未压缩的微代码存储器存储器，其中N

公开(公告)号：US20160104009A1

公开(公告)日：2016-04-14

申请号：US14884502

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN ,  THOMAS A. CRISPIN

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/74 ,  G06F9/30

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor and method are provided for securely decrypting and executing encrypted instructions within a microprocessor. A plurality of master keys are stored in a secure memory. Encrypted instructions are fetched from an instruction cache. A set of one or more master keys are selected from the secure memory based upon an encrypted instruction fetch address. The selected set of master keys or a decryption key derived therefrom is used to decrypt the encrypted instructions fetched from the instruction cache. The decrypted instructions are then securely executed within the microprocessor. In one implementation, the master keys are intervolved with each other to produce a new decryption key with every fetch quantum. Moreover, a new set of master keys is selected with every new block of instructions.

Abstract translation: 提供了微处理器和方法，用于在微处理器内安全解密和执行加密指令。 多个主密钥存储在安全存储器中。 从指令缓存中提取加密指令。 基于加密的指令提取地址从安全存储器中选择一组或多个主密钥。 所选择的一组主密钥或从其导出的解密密钥用于解密从指令高速缓存取出的加密指令。 然后在微处理器内安全地执行解密的指令。 在一个实现中，主密钥彼此相互交织以产生具有每个获取量子的新的解密密钥。 此外，每个新的指令块都选择一组新的主键。

公开(公告)号：US20160105282A1

公开(公告)日：2016-04-14

申请号：US14884416

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN ,  THOMAS A. CRISPIN

IPC: H04L9/08 ,  G06F12/08 ,  G06F12/14

CPC classification number: H04L9/0825 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/6026 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0827 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A secure memory, key expansion logic, and decryption logic are provided for a microprocessor that executes encrypted instructions. The secure memory stores a plurality of decryption key primitives. The key expansion logic selects two or more decryption key primitives from the secure memory and then derives a decryption key from them. The decryption logic uses the decryption key to decrypt an encrypted instruction fetched from the instruction cache. The decryption key primitives are selected on the basis of an encrypted instruction address, one of them is rotated by an amount also determined by the encrypted instruction address, and then they are additively or subtractively accumulated, also on the basis of the encrypted instruction address.

Abstract translation: 为执行加密指令的微处理器提供安全存储器，密钥扩展逻辑和解密逻辑。 安全存储器存储多个解密密钥基元。 密钥扩展逻辑从安全存储器中选择两个或多个解密密钥原语，然后从其中导出解密密钥。 解密逻辑使用解密密钥来解密从指令高速缓存取出的加密指令。 解密密钥基元是根据加密指令地址进行选择的，其中一个被转换了由加密指令地址确定的量，然后也根据加密指令地址进行加法或减法累加。

公开(公告)号：US20160104010A1

公开(公告)日：2016-04-14

申请号：US14884525

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN ,  THOMAS A. CRISPIN

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/74 ,  G06F9/30

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0827 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor conditionally grants a request to switch from a normal execution mode in which encrypted instructions cannot be executed, into a secure execution mode (SEM). Thereafter, the microprocessor executes a plurality of instructions, including a store-key instruction to write a set of one or more cryptographic key values into a secure memory of the microprocessor. After fetching an encrypted program from an instruction cache, the microprocessor decrypts the encrypted program into plaintext instructions using decryption logic within the microprocessor's instruction-processing pipeline.

Abstract translation: 微处理器有条件地授予从加密指令不能被执行的正常执行模式切换到安全执行模式（SEM）的请求。 此后，微处理器执行多个指令，包括将一组一个或多个加密密钥值写入微处理器的安全存储器的存储键指令。 在从指令高速缓存获取加密程序之后，微处理器使用微处理器指令处理流水线内的解密逻辑将加密程序解密为明文指令。