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11.发明申请METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法公开(公告)号：US20100190319A1
公开(公告)日：2010-07-29
申请号：US12754408
申请日：2010-04-05
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译： 提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。 在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。 将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。 然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。 纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。 在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。
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12.发明授权Composite charge storage structure formation in non-volatile memory using etch stop technologies 有权使用蚀刻停止技术在非易失性存储器中形成复合电荷存储结构公开(公告)号：US07615447B2
公开(公告)日：2009-11-10
申请号：US11960498
申请日：2007-12-19
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。
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13.发明申请Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies 有权使用蚀刻停止技术在非易失性存储器中的复合电荷存储结构形成公开(公告)号：US20090163009A1
公开(公告)日：2009-06-25
申请号：US11960498
申请日：2007-12-19
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。
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公开(公告)号：US08222091B2
公开(公告)日：2012-07-17
申请号：US13309857
申请日：2011-12-02
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
摘要翻译： 一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个 的第二轨道，其沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开， 所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。 第一半导体轨道沿第一方向延伸。 第二半导体轨道沿与第一方向不同的第二方向延伸。
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15.发明授权Non-volatile memory fabrication and isolation for composite charge storage structures 有权用于复合电荷存储结构的非易失性存储器制造和隔离公开(公告)号：US07888210B2
公开(公告)日：2011-02-15
申请号：US11960518
申请日：2007-12-19
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译： 制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。 为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。 可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。 在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。 然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。 然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。
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16.发明申请Non-Volatile Memory Fabrication And Isolation For Composite Charge Storage Structures 有权用于复合电荷存储结构的非易失性存储器制造和隔离公开(公告)号：US20090162977A1
公开(公告)日：2009-06-25
申请号：US11960518
申请日：2007-12-19
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译： 制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。 为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。 可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。 在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。 然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。 然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。
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17.发明申请METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法公开(公告)号：US20090155967A1
公开(公告)日：2009-06-18
申请号：US11958941
申请日：2007-12-18
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译： 提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。 在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。 将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。 然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。 纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。 在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。
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18.发明申请公开(公告)号：US20120199898A1
公开(公告)日：2012-08-09
申请号：US13451009
申请日：2012-04-19
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L27/115
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。
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公开(公告)号：US08946803B2
公开(公告)日：2015-02-03
申请号：US11951998
申请日：2007-12-06
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L27/108 , H01L29/423
CPC分类号： H01L21/28273 , H01L27/10844 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.
摘要翻译： 浮动栅极存储器阵列的浮动栅极在位线方向和字线方向都具有倒T形。 使用分离形成浮动栅极的两个多晶硅层的蚀刻停止层形成浮动栅极。 字线在一个示例中在浮动栅极上延伸，并且在另一示例中，字线在浮动栅极之间延伸。
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公开(公告)号：US20120001252A1
公开(公告)日：2012-01-05
申请号：US12827947
申请日：2010-06-30
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L27/115 , H01L21/8246 , H01L21/8247 , H01L29/788 , H01L21/336
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
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