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64 条记录 (耗时 0.032 秒)

    Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation
    6.
    发明申请
    Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation 有权
    具有扁平单元结构和空气间隙隔离的非易失性存储器

    公开(公告)号：US20110309430A1

    公开(公告)日：2011-12-22

    申请号：US13162550

    申请日：2011-06-16

    申请人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

    发明人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

    IPC分类号： H01L29/788 ,  H01L21/764

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649

    摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

    摘要翻译： 高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。 控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。 至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

    Ultrahigh density vertical NAND memory device and method of making thereof
    8.
    发明授权
    Ultrahigh density vertical NAND memory device and method of making thereof 有权
    超高密度垂直NAND存储器件及其制造方法

    公开(公告)号：US08187936B2

    公开(公告)日：2012-05-29

    申请号：US12827947

    申请日：2010-06-30

    申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

    发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

    摘要： A method of making a monolithic three dimensional NAND string. The method includes forming a stack of alternating layers of a first material and a second material over a substrate. The first material includes a conductive or semiconductor control gate material and the second material includes an insulating material. The method also includes etching the stack to form at least one opening in the stack, selectively etching the first material to form first recesses in the first material and forming a blocking dielectric in the first recesses. The method also includes forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric, forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening and forming a semiconductor channel in the at least one opening.

    摘要翻译： 制造单片三维NAND串的方法。 该方法包括在衬底上形成第一材料和第二材料的交替层的叠层。 第一材料包括导电或半导体控制栅极材料，第二材料包括绝缘材料。 该方法还包括蚀刻堆叠以在堆叠中形成至少一个开口，选择性地蚀刻第一材料以在第一材料中形成第一凹槽并在第一凹槽中形成阻挡电介质。 该方法还包括在隔离电介质上的第一凹槽中形成彼此分开的多个离散的电荷存储段，在暴露在至少一个开口中的离散电荷存储段的侧壁上形成隧道电介质，并形成半导体 通道在至少一个开口中。

    Damascene method of making a nonvolatile memory device
    9.
    发明授权
    Damascene method of making a nonvolatile memory device 有权

    公开(公告)号：US08097498B2

    公开(公告)日：2012-01-17

    申请号：US12693322

    申请日：2010-01-25

    申请人： Vinod Robert Purayath ,  George Matamis ,  James Kai ,  Takashi Orimoto

    发明人： Vinod Robert Purayath ,  George Matamis ,  James Kai ,  Takashi Orimoto

    IPC分类号： H01L21/20

    CPC分类号： H01L27/101 ,  H01L27/1021

    摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

    Lithographically space-defined charge storage regions in non-volatile memory
    10.
    发明授权
    Lithographically space-defined charge storage regions in non-volatile memory 有权
    非易失性存储器中的光刻空间定义电荷存储区域

    公开(公告)号：US07807529B2

    公开(公告)日：2010-10-05

    申请号：US11960513

    申请日：2007-12-19

    申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

    发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

    摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.

    摘要翻译： 在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。 牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。 用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。 可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。 较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。 存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域 的第一电荷存储区域。