公开(公告)号：US06340547B1

公开(公告)日：2002-01-22

申请号：US09481032

申请日：2000-01-11

申请人： Ming-Fa Chen ,  Chih-Chien Hung ,  Chia-Hsiang Chen ,  Fu-Tien Wong

发明人： Ming-Fa Chen ,  Chih-Chien Hung ,  Chia-Hsiang Chen ,  Fu-Tien Wong

IPC分类号： G03F900

CPC分类号： G03F9/7003 ,  G03F7/70458 ,  G03F9/7046

摘要： A method of forming circuit patterns on a semiconductor wafer using two different image steppers having nonaligned optical image systems achieves optical alignment of multiple overlays with high accuracy. A first alignment mark is imaged by the first stepper onto a material layer deposited on the wafer, and a second alignment mark is imaged onto a subsequently deposited material layer using the second stepper. Alignment of the two marks, and thus of successively imaged, overlying circuit patterns, is achieved by translating the optical coordinates of the second alignment system into the those of the first alignment system, and then making corresponding two dimensional adjustment of the wafer position relative to the second stepper.

摘要翻译： 使用具有非对准光学图像系统的两个不同的图像步进器在半导体晶片上形成电路图案的方法实现了高精度的多个覆盖层的光学对准。 将第一对准标记由第一步进器成像到沉积在晶片上的材料层上，并且使用第二步进器将第二对准标记成像到随后沉积的材料层上。 通过将第二对准系统的光学坐标转换为第一对准系统的光学坐标，然后相对于第二对准系统的晶片位置进行相应的二维调整来实现两个标记的对准，并且因此连续成像的上覆电路图案的对准 第二步。

公开(公告)号：US5990567A

公开(公告)日：1999-11-23

申请号：US262311

申请日：1999-03-04

申请人： Huan-Chi Tseng ,  Chia-Hsiang Chen ,  Han-Liang Tseng

发明人： Huan-Chi Tseng ,  Chia-Hsiang Chen ,  Han-Liang Tseng

IPC分类号： G03F7/20 ,  G03F7/207 ,  H01L23/544 ,  G01B11/14 ,  G01J1/00 ,  G01N21/00

CPC分类号： G03F7/70641 ,  H01L22/34

摘要： An integrated de-focus pattern provides an effective in-line monitor for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

摘要翻译： 集成的去焦点图案为集成电路晶片的照相处理步骤提供了有效的在线监视器。 在集成电路芯片之间的垂直和水平空间中的集成电路晶片上形成去焦图案。 去焦图案在晶片表面上方的不同高度具有许多不同的测试图案。 去焦点图案放置在整个晶片表面上。 在形成电路芯片的特征的同时形成去焦图形。 去焦图案可以光学分析或使用扫描电子显微镜。

公开(公告)号：US20130166957A1

公开(公告)日：2013-06-27

申请号：US13433556

申请日：2012-03-29

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： G06F11/07

CPC分类号： G06F11/008 ,  G06F11/079

摘要： A system error analysis device which includes a top unit and a storage unit coupled to the top module is mentioned. The storage unit is configured to store each of the input data, each of the output data and each of the bus data transmitted by the top unit. When receiving an interrupting signal, the system error analysis device outputs the input data, the output data and the bus data stored as soon as the interrupting signal is received and the input data, the output data and the bus data stored before the receiving of the interrupting signal. Accordingly, by comparing and analyzing the data output by system error analysis device, the system employing the system error analysis device is able to obtain the reason of the generation of the interrupting signal.

摘要翻译： 提及一种包括顶部单元和耦合到顶部模块的存储单元的系统误差分析装置。 存储单元被配置为存储每个输入数据，每个输出数据和由顶部单元发送的每个总线数据。 当接收到中断信号时，系统误差分析装置在接收到中断信号之后输出存储的输入数据，输出数据和总线数据，并且在接收到中断信号之前存储输入数据，输出数据和总线数据 中断信号。 因此，通过比较和分析由系统误差分析装置输出的数据，采用系统误差分析装置的系统能够获得产生中断信号的原因。

公开(公告)号：US20130132757A1

公开(公告)日：2013-05-23

申请号：US13348082

申请日：2012-01-11

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： G06F1/32

CPC分类号： G06F1/26 ,  G06F1/30 ,  G06F9/4403 ,  G06F11/3031 ,  G06F11/3058

摘要： A power-on controlling method and system are provided. The system includes a power management unit, a voltage regulating module and a power controller. After booting a computer system, the power controller controls the power managing unit to selectively execute a discontinuous mode or a continuous mode according to a selection command, so as to control the voltage regulating module to regulate a system voltage supplied for electric elements in the computer system, thus finishing the system initialization action, and improving the flexibility in monitoring the power of computer system.

摘要翻译： 提供了一种开机控制方法和系统。 该系统包括电源管理单元，电压调节模块和电源控制器。 在引导计算机系统之后，功率控制器控制功率管理单元根据选择命令选择性地执行不连续模式或连续模式，以便控制电压调节模块来调节为计算机中的电气元件提供的系统电压 系统，从而完成系统初始化动作，提高监控电脑系统功能的灵活性。

公开(公告)号：US20130132712A1

公开(公告)日：2013-05-23

申请号：US13348185

申请日：2012-01-11

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： G06F1/28 ,  G06F9/00

CPC分类号： G06F1/30

摘要： A handling device and method for voltage faults applicable for using in a computer system. The handling method includes acquiring a signal of voltage fault. According to the signal of voltage fault and by looking up at tables, an operating status of the computer system corresponding to the signal of voltage fault is acquired, and generating a control signal according to the operating status. Then, the computer system according to the control signal is restarted.

摘要翻译： 适用于计算机系统中使用的电压故障的处理装置和方法。 处理方法包括获取电压故障信号。 根据电压故障的信号，通过查看表，获取与电压故障信号对应的计算机系统的运行状态，并根据运行状态生成控制信号。 然后，重新开始根据控制信号的计算机系统。

公开(公告)号：US20120118386A1

公开(公告)日：2012-05-17

申请号：US13104744

申请日：2011-05-10

申请人： Han-Yi CHEN ,  Chia-Hsiang Chen ,  Huan-Chieh Su ,  Kuo-Liang Liu ,  Tri-Rung Yew

发明人： Han-Yi CHEN ,  Chia-Hsiang Chen ,  Huan-Chieh Su ,  Kuo-Liang Liu ,  Tri-Rung Yew

IPC分类号： H01L31/02 ,  H01B1/08 ,  B82Y99/00

CPC分类号： H01B1/08 ,  B82Y30/00 ,  C01G39/02 ,  C01P2002/54 ,  C01P2004/16 ,  C01P2004/17 ,  C01P2006/40 ,  H01G9/2031 ,  H01G9/2059 ,  H01L31/022466 ,  H01L31/035227 ,  H01L31/03529 ,  H01L31/072 ,  H01L31/1884 ,  H01L51/442 ,  Y02E10/50

摘要： A p-type transparent conductive oxide and a solar cell containing the p-type transparent conducting oxide, wherein the p-type transparent conductive oxide includes a molybdenum trioxide doped with an element having less than six valence electrons, the element is selected from the group consisting of alkali metals, alkaline earth metals, group III elements, group IV, group V, transition elements and their combinations. Doping an element having less than six valence electron results in hole number increase, and thus increasing the hole drift velocity, and making Fermi level closer to the range of p-type materials. Hence, a p-type transparent conductive material is generated. This p-type transparent conducting oxide not only has high electron hole drift velocity, low resistivity, but also reaches a transmittance of 88% in the visible wavelength range, and therefore it is very suitable to be used in solar cells.

摘要翻译： p型透明导电氧化物和含有p型透明导电氧化物的太阳能电池，其中p型透明导电氧化物包括掺杂有少于6价电子的元素的三氧化钼，该元素选自 由碱金属，碱土金属，III族元素，IV族，V族，过渡元素及其组合组成。 掺杂具有小于6价电子的元素导致孔数增加，从而增加空穴漂移速度，并使费米能级更接近p型材料的范围。 因此，产生p型透明导电材料。 该p型透明导电氧化物不仅具有高的电子空穴漂移速度，低电阻率，而且在可见光波长范围内也达到88％的透射率，因此非常适用于太阳能电池。

公开(公告)号：US06984193B2

公开(公告)日：2006-01-10

申请号：US10751973

申请日：2004-01-07

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： A63B22/02

CPC分类号： A63B22/0023 ,  A63B2208/12 ,  A63B2210/50

摘要： A treadmill with a lifting device includes a main frame, a platform pivotally connected to the main frame and a lifting device mounted to the main frame and the platform. The lifting device includes a power supplier mounted to the main frame and a folding structure connected to the main frame and the platform. The folding structure includes a buckle device for holding the platform in place when the platform is fully lifted.

摘要翻译： 具有提升装置的跑步机包括主框架，枢转地连接到主框架的平台和安装到主框架和平台的提升装置。 提升装置包括安装在主框架上的电源和连接到主框架和平台的折叠结构。 折叠结构包括用于当平台完全提升时将平台保持在适当位置的带扣装置。

公开(公告)号：US06330355B1

公开(公告)日：2001-12-11

申请号：US09283851

申请日：1999-04-01

申请人： Chia-Hsiang Chen ,  Chih-Chien Hung ,  Han-Ming Sheng ,  Hsiang-Chung Liu ,  Chun-Mei Lee ,  De-Ming Liang ,  Li-Kong Turn ,  Ming-Huei Tseng

发明人： Chia-Hsiang Chen ,  Chih-Chien Hung ,  Han-Ming Sheng ,  Hsiang-Chung Liu ,  Chun-Mei Lee ,  De-Ming Liang ,  Li-Kong Turn ,  Ming-Huei Tseng

IPC分类号： G06K932

CPC分类号： G03F7/70633

摘要： A frame layout and method for determining the overlay accuracy of a first chip image relative to a second chip image when the first and second chip images are used to form a single chip. One embodiment employs a vernier scale in two orthoginal directions included in the scribeline of both the first chip image and the second chip image. Another embodiment employs a box in box pattern included in the scribeline of both the first chip image and the second chip image. A layer of photoresist on an integrated circuit wafer is exposed with the first and second chip image and the associated monitor images. When the photoresist is developed the overlay accuracy of the first chip image relative to the second chip image can be determined directly from the monitor images in the photoresist.

摘要翻译： 一种帧布局和方法，用于当第一和第二芯片图像用于形成单个芯片时，确定第一芯片图像相对于第二芯片图像的叠加精度。 一个实施例在包括在第一芯片图像和第二芯片图像的划线中的两个正交方向上使用游标刻度。 另一个实施例采用包括在第一芯片图像和第二芯片图像的划线中的盒子模式。 集成电路晶片上的一层光致抗蚀剂用第一和第二芯片图像和相关联的监视器图像曝光。 当光致抗蚀剂显影时，可以直接从光致抗蚀剂中的监视器图像确定第一芯片图像相对于第二芯片图像的覆盖精度。

公开(公告)号：US08643006B2

公开(公告)日：2014-02-04

申请号：US13163727

申请日：2011-06-20

申请人： Chia-Hsiang Chen ,  Ming-Chin Hung ,  Chun-Hao Tu ,  Wei-Ting Lin ,  Jiun-Jye Chang

发明人： Chia-Hsiang Chen ,  Ming-Chin Hung ,  Chun-Hao Tu ,  Wei-Ting Lin ,  Jiun-Jye Chang

IPC分类号： H01L29/786

CPC分类号： H01L29/4908 ,  H01L29/7869

摘要： A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.

摘要翻译： 提供薄膜晶体管。 薄膜晶体管包括衬底，栅极，栅极绝缘层，源极和漏极，沟道层以及第一和第二图案化钝化层。 栅极设置在基板上。 栅极绝缘层设置在栅极上。 源极和漏极设置在栅极绝缘层上。 沟道层设置在源极和漏极之上或之下，其中沟道层的一部分暴露在源极和漏极之间。 第一图案化钝化层设置在沟道层的部分上，其中第一图案化钝化层包括金属氧化物，第一图案化钝化层的厚度范围为50埃至300埃。 第二图案化钝化层覆盖第一图案化钝化层，栅极绝缘层以及源极和漏极。

公开(公告)号：US08558606B2

公开(公告)日：2013-10-15

申请号：US13337816

申请日：2011-12-27

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： H03K17/16

CPC分类号： H03K5/1254

摘要： A debounce apparatus and a method thereof are provided, which includes a debounce module, a register and a timer. The debounce module receives an input signal and eliminates a bounce phenomenon of the input signal within a transient-time of the state-changing of the input signal to produce a debounce signal. The register outputs an output signal according to the value stored in the register. When the input signal changes its state, the timer starts time-counting according to a counting-value of settling-time; when the debounce signal changes its state, the timer recounts time; and when time-counting is ended and when the value corresponding to the debounce signal is different from the register's value, the register's value is updated by the value corresponding to the debounce signal. In this way, the apparatus can eliminate the system misjudgement problem caused by occurred voltage level errors in the stable state.

摘要翻译： 提供一种去抖动装置及其方法，其包括去抖模块，寄存器和定时器。 去抖模块在输入信号的状态变化的瞬态时间内接收输入信号并消除输入信号的反弹现象以产生去抖动信号。 寄存器根据存储在寄存器中的值输出输出信号。 当输入信号改变其状态时，定时器根据建立时间的计数值开始计时; 当去抖信号改变其状态时，定时器重新计时; 并且当计时结束并且当与去抖动信号相对应的值与寄存器的值不同时，寄存器的值被更新为对应于去抖动信号的值。 以这种方式，该装置可以消除在稳定状态下由发生的电压电平误差引起的系统误判问题。