公开(公告)号：US08726074B2

公开(公告)日：2014-05-13

申请号：US13348185

申请日：2012-01-11

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： G06F11/00

CPC分类号： G06F1/30

摘要： A handling device and method for voltage faults applicable for using in a computer system. The handling method includes acquiring a signal of voltage fault. According to the signal of voltage fault and by looking up at tables, an operating status of the computer system corresponding to the signal of voltage fault is acquired, and generating a control signal according to the operating status. Then, the computer system according to the control signal is restarted.

摘要翻译： 适用于计算机系统中使用的电压故障的处理装置和方法。 处理方法包括获取电压故障信号。 根据电压故障的信号，通过查看表，获取与电压故障信号对应的计算机系统的运行状态，并根据运行状态生成控制信号。 然后，重新开始根据控制信号的计算机系统。

公开(公告)号：US20130138939A1

公开(公告)日：2013-05-30

申请号：US13351996

申请日：2012-01-17

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： G06F9/00

CPC分类号： G06F11/1417 ,  G06F11/0757 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/321

摘要： A method for processing booting errors for a computer having multiple voltage regulator downs (VRDs) includes reading a boot sequence including multiple power-on stages, and each power-on stage corresponds to a boot voltage and one of the VRDs; performing the power-on stages according to the boot sequence, and determining whether an output voltage of the VRD corresponding to each power-on stage is equal to the corresponding boot voltage; and when the output voltage of any one of the VRDs is not equal to the corresponding boot voltage, performing a debugging procedure.

摘要翻译： 一种用于处理具有多个电压调节器降压（VRD）的计算机的引导错误的方法包括读取包括多个上电级的引导序列，并且每个上电阶段对应于引导电压和VRD中的一个; 根据引导顺序执行上电阶段，并且确定与每个上电阶段相对应的VRD的输出电压是否等于相应的引导电压; 并且当任何一个VRD的输出电压不等于相应的引导电压时，执行调试过程。

公开(公告)号：US20120132914A1

公开(公告)日：2012-05-31

申请号：US13045502

申请日：2011-03-10

申请人： Chia-Hsiang Chen ,  Shih-Hsien Tseng ,  Ming-Chin Hung ,  Chun-Hao Tu ,  Wei-Ting Lin ,  Jiun-Jye Chang

发明人： Chia-Hsiang Chen ,  Shih-Hsien Tseng ,  Ming-Chin Hung ,  Chun-Hao Tu ,  Wei-Ting Lin ,  Jiun-Jye Chang

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/45 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

摘要： An oxide semiconductor thin film transistor structure includes a substrate, a gate electrode disposed on the substrate, a semiconductor insulating layer disposed on the substrate and the gate electrode, an oxide semiconductor layer disposed on the semiconductor insulating layer, a patterned semiconductor layer disposed on the oxide semiconductor layer, and a source electrode and a drain electrode respectively disposed on the patterned semiconductor layer. The source electrode and the drain electrode are made of a metal layer.

摘要翻译： 氧化物半导体薄膜晶体管结构包括基板，设置在基板上的栅极电极，设置在基板上的半导体绝缘层和栅电极，设置在半导体绝缘层上的氧化物半导体层，设置在该半导体绝缘层上的图案化半导体层 氧化物半导体层，以及分别设置在图案化半导体层上的源电极和漏电极。 源电极和漏电极由金属层制成。

公开(公告)号：US07081180B2

公开(公告)日：2006-07-25

申请号：US10729944

申请日：2003-12-09

申请人： Jyh-Luen Chen ,  Wen-Tung Wang ,  Shuo-Wei Liang ,  Chia-Hsiang Chen

发明人： Jyh-Luen Chen ,  Wen-Tung Wang ,  Shuo-Wei Liang ,  Chia-Hsiang Chen

IPC分类号： B32B37/20 ,  B32B15/04

CPC分类号： B32B37/20 ,  B32B38/0004 ,  B32B2037/243 ,  B32B2038/042 ,  B32B2457/20 ,  G02F1/133305 ,  G02F1/133365 ,  G02F1/1341 ,  Y10T156/1052 ,  Y10T156/1074 ,  Y10T156/1084 ,  Y10T156/1085 ,  Y10T156/1309

摘要： A process for fabricating passive plastic displays, comprising the steps of: adopting a roll-to-roll coating machine for fabricating a bottom substrate having a fist patterned conducting line, fabricating a top substrate having a second patterned conducting line and an active area of polymeric liquid crystal on the surface of the top substrate by means of a roll-to-roll coating machine, and sealing the top and the bottom substrates by means of a roll-to-roll coating machine to form a plurality of display panels. Due to the continuous fabrication of the present invention with the low-cost apparatuses, applications of the plastic displays in the low-end products can be accelerated.

摘要翻译： 一种用于制造无源塑料显示器的方法，包括以下步骤：采用辊对辊涂布机来制造具有第一图案化导电线的底部衬底，制造具有第二图案化导电线的顶部衬底和聚合物的有源区域 通过辊对辊涂布机在顶部基板的表面上形成液晶，并通过辊对辊涂布机密封顶部和底部基板以形成多个显示面板。 由于利用低成本设备连续制造本发明，可以加速低端产品中的塑料显示器的应用。

公开(公告)号：US07045817B2

公开(公告)日：2006-05-16

申请号：US10964611

申请日：2004-10-15

申请人： Cheng-Chung Chen ,  Yu-Chang Sun ,  Yi-Hsun Huang ,  Chien-Wei Wu ,  Shuo-Wei Liang ,  Chia-Hsiang Chen ,  Chi-Shen Lee ,  Chai-Yuan Sheu ,  Yu-Chi Lee ,  Te-Ming Chu ,  Cheng-Hsing Chen

发明人： Cheng-Chung Chen ,  Yu-Chang Sun ,  Yi-Hsun Huang ,  Chien-Wei Wu ,  Shuo-Wei Liang ,  Chia-Hsiang Chen ,  Chi-Shen Lee ,  Chai-Yuan Sheu ,  Yu-Chi Lee ,  Te-Ming Chu ,  Cheng-Hsing Chen

IPC分类号： H01L31/0376 ,  H01L29/04 ,  G02F27/12 ,  G02F1/1343 ,  G02F1/136

CPC分类号： H01L29/78669 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66765

摘要： The invention provides a TFT electrode structure and its manufacturing method that can prevent metal diffusion occurring in the fabrication of a TFT, and thereby reduce the risk of contamination of the chemical vapor deposition process due to metallic ion diffusion. The transparent pixel electrode is formed after the gate electrode metal so that the pixel transparent electrode can be used as a barrier layer to prevent metal diffusion under high temperature from the gate electrode metal to adjacent insulating layers or the active layer. Further, the method used to form the transparent pixel electrode is a low-temperature physical vapor deposition process, which affected less by the processing environment, and the transparent pixel electrode is a conductive layer that is not affected by metal diffusion.

摘要翻译： 本发明提供一种能够防止TFT制造中发生金属扩散的TFT电极结构及其制造方法，从而降低由金属离子扩散引起的化学气相沉积工艺的污染风险。 透明像素电极形成在栅电极金属之后，使得像素透明电极可以用作阻挡层，以防止在高温下从栅电极金属到相邻绝缘层或有源层的金属扩散。 此外，用于形成透明像素电极的方法是低温物理气相沉积工艺，其受处理环境影响较小，并且透明像素电极是不受金属扩散影响的导电层。

公开(公告)号：US06340547B1

公开(公告)日：2002-01-22

申请号：US09481032

申请日：2000-01-11

申请人： Ming-Fa Chen ,  Chih-Chien Hung ,  Chia-Hsiang Chen ,  Fu-Tien Wong

发明人： Ming-Fa Chen ,  Chih-Chien Hung ,  Chia-Hsiang Chen ,  Fu-Tien Wong

IPC分类号： G03F900

CPC分类号： G03F9/7003 ,  G03F7/70458 ,  G03F9/7046

摘要： A method of forming circuit patterns on a semiconductor wafer using two different image steppers having nonaligned optical image systems achieves optical alignment of multiple overlays with high accuracy. A first alignment mark is imaged by the first stepper onto a material layer deposited on the wafer, and a second alignment mark is imaged onto a subsequently deposited material layer using the second stepper. Alignment of the two marks, and thus of successively imaged, overlying circuit patterns, is achieved by translating the optical coordinates of the second alignment system into the those of the first alignment system, and then making corresponding two dimensional adjustment of the wafer position relative to the second stepper.

摘要翻译： 使用具有非对准光学图像系统的两个不同的图像步进器在半导体晶片上形成电路图案的方法实现了高精度的多个覆盖层的光学对准。 将第一对准标记由第一步进器成像到沉积在晶片上的材料层上，并且使用第二步进器将第二对准标记成像到随后沉积的材料层上。 通过将第二对准系统的光学坐标转换为第一对准系统的光学坐标，然后相对于第二对准系统的晶片位置进行相应的二维调整来实现两个标记的对准，并且因此连续成像的上覆电路图案的对准 第二步。

公开(公告)号：US5990567A

公开(公告)日：1999-11-23

申请号：US262311

申请日：1999-03-04

申请人： Huan-Chi Tseng ,  Chia-Hsiang Chen ,  Han-Liang Tseng

发明人： Huan-Chi Tseng ,  Chia-Hsiang Chen ,  Han-Liang Tseng

IPC分类号： G03F7/20 ,  G03F7/207 ,  H01L23/544 ,  G01B11/14 ,  G01J1/00 ,  G01N21/00

CPC分类号： G03F7/70641 ,  H01L22/34

摘要： An integrated de-focus pattern provides an effective in-line monitor for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

摘要翻译： 集成的去焦点图案为集成电路晶片的照相处理步骤提供了有效的在线监视器。 在集成电路芯片之间的垂直和水平空间中的集成电路晶片上形成去焦图案。 去焦图案在晶片表面上方的不同高度具有许多不同的测试图案。 去焦点图案放置在整个晶片表面上。 在形成电路芯片的特征的同时形成去焦图形。 去焦图案可以光学分析或使用扫描电子显微镜。

公开(公告)号：US20130166957A1

公开(公告)日：2013-06-27

申请号：US13433556

申请日：2012-03-29

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： G06F11/07

CPC分类号： G06F11/008 ,  G06F11/079

摘要： A system error analysis device which includes a top unit and a storage unit coupled to the top module is mentioned. The storage unit is configured to store each of the input data, each of the output data and each of the bus data transmitted by the top unit. When receiving an interrupting signal, the system error analysis device outputs the input data, the output data and the bus data stored as soon as the interrupting signal is received and the input data, the output data and the bus data stored before the receiving of the interrupting signal. Accordingly, by comparing and analyzing the data output by system error analysis device, the system employing the system error analysis device is able to obtain the reason of the generation of the interrupting signal.

摘要翻译： 提及一种包括顶部单元和耦合到顶部模块的存储单元的系统误差分析装置。 存储单元被配置为存储每个输入数据，每个输出数据和由顶部单元发送的每个总线数据。 当接收到中断信号时，系统误差分析装置在接收到中断信号之后输出存储的输入数据，输出数据和总线数据，并且在接收到中断信号之前存储输入数据，输出数据和总线数据 中断信号。 因此，通过比较和分析由系统误差分析装置输出的数据，采用系统误差分析装置的系统能够获得产生中断信号的原因。

公开(公告)号：US20130132757A1

公开(公告)日：2013-05-23

申请号：US13348082

申请日：2012-01-11

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： G06F1/32

CPC分类号： G06F1/26 ,  G06F1/30 ,  G06F9/4403 ,  G06F11/3031 ,  G06F11/3058

摘要： A power-on controlling method and system are provided. The system includes a power management unit, a voltage regulating module and a power controller. After booting a computer system, the power controller controls the power managing unit to selectively execute a discontinuous mode or a continuous mode according to a selection command, so as to control the voltage regulating module to regulate a system voltage supplied for electric elements in the computer system, thus finishing the system initialization action, and improving the flexibility in monitoring the power of computer system.

摘要翻译： 提供了一种开机控制方法和系统。 该系统包括电源管理单元，电压调节模块和电源控制器。 在引导计算机系统之后，功率控制器控制功率管理单元根据选择命令选择性地执行不连续模式或连续模式，以便控制电压调节模块来调节为计算机中的电气元件提供的系统电压 系统，从而完成系统初始化动作，提高监控电脑系统功能的灵活性。

公开(公告)号：US20130132712A1

公开(公告)日：2013-05-23

申请号：US13348185

申请日：2012-01-11

申请人： Chia-Hsiang Chen

发明人： Chia-Hsiang Chen

IPC分类号： G06F1/28 ,  G06F9/00

CPC分类号： G06F1/30

摘要： A handling device and method for voltage faults applicable for using in a computer system. The handling method includes acquiring a signal of voltage fault. According to the signal of voltage fault and by looking up at tables, an operating status of the computer system corresponding to the signal of voltage fault is acquired, and generating a control signal according to the operating status. Then, the computer system according to the control signal is restarted.

摘要翻译： 适用于计算机系统中使用的电压故障的处理装置和方法。 处理方法包括获取电压故障信号。 根据电压故障的信号，通过查看表，获取与电压故障信号对应的计算机系统的运行状态，并根据运行状态生成控制信号。 然后，重新开始根据控制信号的计算机系统。