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公开(公告)号：US20130151837A1
公开(公告)日：2013-06-13
申请号：US13315407
申请日：2011-12-09
IPC分类号： G06F9/00
CPC分类号： G06F9/542 , G06F9/4812 , G06F11/1438 , G06F11/3409 , G06F2209/481
摘要： A method, system or computer usable program product for an operating system (OS) enabling an application direct control of a performance monitoring unit (PMU) including enabling the PMU to notify the application when a PMU exception occurs without interrupting the OS by controllably encoding a redirect field in an OS accessible control register, and enabling the application to reinitialize the PMU after the PMU exception.
摘要翻译： 一种用于操作系统（OS）的方法，系统或计算机可用程序产品，其能够直接控制性能监视单元（PMU），包括当PMU异常发生时使PMU通知应用程序，而不会通过可控编码来中断OS 重定向字段在OS可访问控制寄存器中，并使应用程序在PMU异常之后重新初始化PMU。
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公开(公告)号：US20130142301A1
公开(公告)日：2013-06-06
申请号：US13312715
申请日：2011-12-06
IPC分类号： H03K23/00
CPC分类号： G06F11/2284 , G06F11/0724 , G06F11/076 , G06F11/3024 , G06F11/3058 , G06F11/3082 , G06F11/3409 , G06F11/348 , G06F2201/835 , G06F2201/86 , G06F2201/88
摘要： Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.
摘要翻译： 电子设备中的特定事件的发生通过在每次发生特定事件的可变数量时增加事件计数器来计数，并且随着总计数增加而自动增加该变量数。 每当计数尾数溢出时，可变数（预分频值）可根据可编程的计数器基数在几何上增加。 事件计数器由此提供硬件实现的自动预分频，同时显着减少支持非常大的计数范围所需的接口位数，并在非常大的事件计数下保持高精度。
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公开(公告)号：US20120084511A1
公开(公告)日：2012-04-05
申请号：US12897008
申请日：2010-10-04
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/383 , G06F12/0897 , G06F2212/6024
摘要： A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyses the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the infectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.
摘要翻译： 信息处理系统（IHS）的处理器在指令处理期间响应于需求负载启动L3高速缓存预取操作。 处理器随机选择L3高速缓存预取作为目标预取指令进行跟踪。 处理器发起L1高速缓存目标预取操作，并将所得到的目标预取指令存储在L1高速缓存中。 如果需求负载到达，则处理器分析目标预取指令的有效性并确定预取数据的来源。 如果请求没有到达，则处理器测试以确定特定预取指令是否在高速缓存中超时并且识别预取操作的感染性。 处理器随机抽取多个预取操作，并生成预取有效性和其他有用的预取信息的历史记录。 处理器存储预取有效性信息以便能够减少或去除无效的预取操作。
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14.发明授权公开(公告)号：US08091073B2
公开(公告)日：2012-01-03
申请号：US11758031
申请日：2007-06-05
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F9/44
CPC分类号： G06F11/36
摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.
摘要翻译： 提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。 针对一组阶段中的每个阶段计算相位指令预算。 相位指令预算基于与每个阶段相关联的权重和全局指令预算。 为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。 确定区间指标集内的指令是否符合全球指令预算。 响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。
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15.发明授权Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information 有权使用包括数据相关信息的增强型基本块向量来评估集成电路设计性能的方法和装置公开(公告)号：US07844928B2
公开(公告)日：2010-11-30
申请号：US11972747
申请日：2008-01-11
申请人： Robert H. Bell , Thomas W. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell , Thomas W. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples. Designers use the test system with benchmarking software to evaluate IC design model modifications by using the representative reduced application software program.
摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行应用软件的IC基准软件程序。 基准软件包括跟踪，模拟点，聚类和其他程序。 IC设计人员利用基准软件来评估用户用户软件应用的IC设计的性能特征。 基准软件从应用软件的指令轨迹生成基本块向量BBV。 基准软件分析数据相关信息，它附加到BBV以创建增强型BBV或EBBV。 基准软件可以在一个聚类图中绘制EBBV信息，并选择一个EBBV子集作为每个程序阶段的代表性样本。 基准测试软件从代表性的EBBV样本中生成一个减少的应用软件程序。 设计人员使用带有基准测试软件的测试系统，通过使用代表性的减少应用软件程序来评估IC设计模型修改。
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16.发明申请Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information 有权使用基本块向量和包含微体系结构信息的飞越向量评估集成电路设计模型性能的方法和装置公开(公告)号：US20090199138A1
公开(公告)日：2009-08-06
申请号：US12026141
申请日：2008-02-05
申请人： Robert H. Bell , Thomas W. Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell , Thomas W. Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F11/3457 , G06F11/3428
摘要： A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method. Designers use the test system with test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的IC测试应用采样软件程序。 测试应用采样软件包括跟踪，仿真点，CPI错误，聚类等程序。 IC设计人员利用测试应用程序采样软件，通过测试软件应用来评估IC设计的性能特征。 测试应用采样软件从测试应用软件的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。 测试应用程序采样软件分析其用于生成FBV的微体系结构依赖信息。 测试应用采样软件使用指令预算方法从BBV和FBV数据生成降低的代表性测试应用软件程序。 设计人员使用带有测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。
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公开(公告)号：US20140075164A1
公开(公告)日：2014-03-13
申请号：US13610958
申请日：2012-09-12
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： A method and system are disclosed for sampling instructions executing on a computer processor. A computer processor determines a number of times a specified event has occurred within a specified temporal window. The computer processor determines to mark an instruction to be executed for monitoring based on the number of times the specified event has occurred within the temporal window, and in response, the computer processor marks the instruction.
摘要翻译： 公开了一种用于在计算机处理器上执行的采样指令的方法和系统。 计算机处理器确定在指定的时间窗口内发生指定事件的次数。 计算机处理器根据在时间窗口内发生的指定事件的次数来确定要执行的用于监视的指令，并且作为响应，计算机处理器标记指令。
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18.发明授权Initiating assist thread upon asynchronous event for processing simultaneously with controlling thread and updating its running status in status register 有权在异步事件时启动辅助线程，同时处理控制线程并更新状态寄存器中的运行状态公开(公告)号：US08667253B2
公开(公告)日：2014-03-04
申请号：US12849903
申请日：2010-08-04
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/4812 , G06F9/4843
摘要： A processor of a data processing system executes a controlling thread of a program and detects occurrence of a particular asynchronous event during execution of the controlling thread of the program. In response to occurrence of the particular asynchronous event during execution of the controlling thread of the program, the processor initiates execution of an assist thread of the program such that the processor simultaneously executes the assist thread and controlling thread of the program.
摘要翻译： 数据处理系统的处理器执行程序的控制线程，并且在执行程序的控制线程期间检测特定的异步事件的发生。 响应于在执行程序的控制线程期间发生特定的异步事件，处理器启动程序的辅助线程的执行，使得处理器同时执行辅助线程并控制程序的线程。
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19.发明授权Workload performance projection via surrogate program analysis for future information handling systems 失效通过代理程序分析进行未来信息处理系统的工作负载性能预测公开(公告)号：US08527956B2
公开(公告)日：2013-09-03
申请号：US12343467
申请日：2008-12-23
申请人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
发明人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
IPC分类号： G06F9/44
CPC分类号： G06F11/3419 , G06F11/3414 , G06F11/3457 , G06F2201/865 , G06F2201/88
摘要： A performance projection system includes a test IHS and multiple currently existing IHSs. The performance projection system includes user application software and surrogate programs that execute on currently existing IHSs. The performance projection system measures user application software and surrogate program performance during execution on currently existing IHSs. The performance projection systems measures runtime program performance during execution of surrogate programs on a future semiconductor die IC design model or virtualized future system. Designers normalize and compare surrogate program runtime performance data with user application software performance data. Designers un-normalize the normalized runtime performance data to generate a projection of runtime performance on the future system.
摘要翻译： 性能投影系统包括测试IHS和多个当前存在的IHS。 性能投影系统包括在当前存在的IHS上执行的用户应用软件和代理程序。 性能投影系统在目前现有的IHSs的执行过程中测量用户应用软件和代理程序性能。 性能投影系统在未来的半导体芯片IC设计模型或虚拟化未来系统执行替代程序期间测量运行时程序性能。 设计师将代理程序运行时性能数据与用户应用软件性能数据进行规范化和比较。 设计师对规范化的运行时性能数据进行非规范化，以生成对未来系统的运行时性能的投影。
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公开(公告)号：US20110154352A1
公开(公告)日：2011-06-23
申请号：US12645768
申请日：2009-12-23
申请人： Donald R. DESOTA , Rajendra D. Panda , Venkat R. Indukuru , Joseph H. Robichaux , Robert H. Bell, JR. , Steven P. Hartman
发明人： Donald R. DESOTA , Rajendra D. Panda , Venkat R. Indukuru , Joseph H. Robichaux , Robert H. Bell, JR. , Steven P. Hartman
CPC分类号： G06F12/0646 , G06F9/5011 , G06F9/5083 , G06F13/16 , G06F2212/1016
摘要： According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold. The method also includes monitoring memory databus utilization for the plurality of processors and, in response to determining that memory databus utilization for at least one of the processors is below its threshold, reallocating at least a portion of unused databus utilization from the at least one processor to at least one of the other processors.
摘要翻译： 根据本公开的一个方面，公开了一种用于管理存储器存取的方法和技术。 该方法包括为数据处理系统的多个处理器中的每个处理器设置存储器数据总线利用阈值，以将数据处理系统的存储器数据总线利用维持在系统阈值以下。 该方法还包括监视多个处理器的存储器数据总线利用率，并且响应于确定至少一个处理器的存储器数据总线利用率低于其阈值，从至少一个处理器重新分配未使用的数据总线利用的至少一部分 到至少一个其他处理器。
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