公开(公告)号：US20080093634A1

公开(公告)日：2008-04-24

申请号：US11960051

申请日：2007-12-19

申请人： William Clark ,  Edward Nowak

发明人： William Clark ,  Edward Nowak

IPC分类号： H01L31/119 ,  H01L31/18

CPC分类号： H01L29/78648

摘要： Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.

摘要翻译： 公开了使用绝缘体上硅（SOI）技术检测电离辐射的结构和方法。 在一个实施例中，本发明包括具有在衬底上形成的掩埋绝缘体层的衬底和形成在掩埋绝缘体层上的有源层。 活性层可能完全耗尽。 在有源层上形成晶体管，并且包括第一栅极导体，第一栅极电介质和源极/漏极扩散区。 第一栅极导体可以包括具有基本（或完全）耗尽的掺杂浓度的材料，使得其具有比诸如本征多晶硅的掺杂多晶硅更高的电阻率。 第二栅极导体形成在掩埋绝缘体层下方，并提供对应于第二栅极导体的第二栅极电介质。 第一栅极导体和第二栅极导体之间​​的沟道区域由第二栅极导体（背栅极）控制，使得其作为辐射检测器。

公开(公告)号：US20070258503A1

公开(公告)日：2007-11-08

申请号：US11381427

申请日：2006-05-03

申请人： William Clark, Jr. ,  Edward Nowak

发明人： William Clark, Jr. ,  Edward Nowak

IPC分类号： G01K15/00 ,  G01K11/00 ,  G01K7/00

CPC分类号： G01K7/015 ,  G01K7/22 ,  G01K15/00

摘要： Disclosed are embodiments of an improved on-chip temperature sensing circuit, based on bolometry, which provides self calibration of the on-chip temperature sensors for ideality and an associated method of sensing temperature at a specific on-chip location. The circuit comprises a temperature sensor, an identical reference sensor with a thermally coupled heater and a comparator. The comparator is adapted to receive and compare the outputs from both the temperature and reference sensors and to drive the heater with current until the outputs match. Based on the current forced into the heater, the temperature rise of the reference sensor can be calculated, which in this state, is equal to that of the temperature sensor.

摘要翻译： 公开了一种改进的片上温度感测电路的实施例，其基于速率测量，其提供用于理想的片上温度传感器的自校准以及在特定片上位置处感测温度的相关联的方法。 该电路包括温度传感器，具有热耦合加热器的相同参考传感器和比较器。 比较器适用于接收和比较来自温度和参考传感器的输出，并用电流驱动加热器直到输出匹配。 基于被迫进入加热器的电流，可以计算参考传感器的温度上升，在该状态下，其温度等于温度传感器的温升。

公开(公告)号：US20070122957A1

公开(公告)日：2007-05-31

申请号：US11164651

申请日：2005-11-30

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

IPC分类号： H01L21/8234 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

摘要翻译： 为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或 接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化 的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

公开(公告)号：US20060231881A1

公开(公告)日：2006-10-19

申请号：US11427031

申请日：2006-06-28

申请人： William Clark ,  Edward Nowak

发明人： William Clark ,  Edward Nowak

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818

摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.

摘要翻译： 公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。 这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。 较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。 包括与栅极电介质不同的材料的盖可以位于鳍片上方。

公开(公告)号：US20060054978A1

公开(公告)日：2006-03-16

申请号：US11264446

申请日：2005-11-01

申请人： William Clark ,  Edward Nowak

发明人： William Clark ,  Edward Nowak

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818

摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.

摘要翻译： 公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。 这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。 较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。 包括与栅极电介质不同的材料的盖可以位于鳍片上方。

公开(公告)号：US20050205944A1

公开(公告)日：2005-09-22

申请号：US10708674

申请日：2004-03-18

申请人： William Clark ,  Edward Nowak

发明人： William Clark ,  Edward Nowak

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818

摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.

摘要翻译： 公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。 这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。 较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。 包括与栅极电介质不同的材料的盖可以位于鳍片上方。

公开(公告)号：US20120119681A1

公开(公告)日：2012-05-17

申请号：US12946682

申请日：2010-11-15

申请人： Ken Seidl ,  Edward Nowak ,  Paul Li

发明人： Ken Seidl ,  Edward Nowak ,  Paul Li

IPC分类号： H05B37/00

CPC分类号： H05B37/0272

摘要： The present invention provides switches and sensors that automatically turn on and/or off an associated device. In particular, the present invention provides lighting devices containing switches and sensors associated with the device that power/depower the device and systems and objects containing the device.

摘要翻译： 本发明提供了自动打开和/或关闭相关设备的开关和传感器。 特别地，本发明提供了包含与该装置相关联的开关和传感器的照明装置，其对设备和包含该装置的系统和对象进行功率/耗尽。

公开(公告)号：US20080113476A1

公开(公告)日：2008-05-15

申请号：US12014850

申请日：2008-01-16

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78687

摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.

摘要翻译： 本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。 该器件包括在体硅衬底上的鳍式晶体管。 鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。 外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。 诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。 此外，鳍型晶体管在其顶面包括厚氧化物构件。 翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

公开(公告)号：US20080042205A1

公开(公告)日：2008-02-21

申请号：US11877865

申请日：2007-10-24

申请人： Edward Nowak

发明人： Edward Nowak

IPC分类号： H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/743 ,  H01L21/84 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/6675 ,  H01L29/78636 ,  H01L29/78648 ,  Y10S438/914

摘要： A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.

摘要翻译： 提供了一种使用不太长或昂贵的处理步骤来制造具有优异的短沟道特性和减小电容的高性能平面背栅CMOS结构的方法。 还提供了利用本发明的方法形成的高性能平面背栅CMOS结构。 该方法包括在基板的上表面形成开口。 此后，通过开口在衬底中形成掺杂剂区域。 根据本发明的方法，掺杂剂区域限定本发明结构的背栅导体。 接下来，在开口内形成具有至少一部分的前门导体。

公开(公告)号：US20070293031A1

公开(公告)日：2007-12-20

申请号：US11847384

申请日：2007-08-30

申请人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

发明人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

IPC分类号： H01L21/3205

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。