公开(公告)号：US07903379B2

公开(公告)日：2011-03-08

申请号：US11831420

申请日：2007-07-31

申请人： Michael D. Chaine ,  Manny K. F. Ma

发明人： Michael D. Chaine ,  Manny K. F. Ma

IPC分类号： H02H9/00

CPC分类号： H01L29/7831 ,  H01L27/0266 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/41725

摘要： A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.

摘要翻译： 描述了包括形成在两个晶体管之间的共享区域中的屏障的级联I / O驱动器。 屏障区域允许I / O驱动程序设计为主要满足I / O要求。 因此，实现了改进的操作速度。 描述了包括与ESD装置并联的I / O驱动器的系统。 在一个实施例中，在ESD开始导通之后，I / O驱动器可以辅助静电装置放电静电。

公开(公告)号：US06462380B1

公开(公告)日：2002-10-08

申请号：US09695832

申请日：2000-10-25

申请人： Charvaka Duvvury ,  Michael D. Chaine

发明人： Charvaka Duvvury ,  Michael D. Chaine

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： A structure is designed with a lightly doped substrate (316) having a first conductivity type and a face. A first lightly doped region (314) has a second conductivity type and is formed within the lightly doped substrate. A first heavily doped region (308) has the first conductivity type and is formed at the face and extends to a first depth within the first lightly doped region. A second heavily doped region (312) has the second conductivity type and is formed at the face abutting the first heavily doped region. The second heavily doped region extends to a second depth and is at least partly within the first lightly doped region. A first isolation region (304) is formed at the face, abutting at least one of the first and second heavily doped regions. The first isolation region extends to a third depth that is greater than either of the first and the second depths.

摘要翻译： 结构被设计有具有第一导电类型和面的轻掺杂衬底（316）。 第一轻掺杂区域（314）具有第二导电类型并且形成在轻掺杂衬底内。 第一重掺杂区域（308）具有第一导电类型并且形成在面部并且延伸到第一轻掺杂区域内的第一深度。 第二重掺杂区域（312）具有第二导电类型并且形成在邻接第一重掺杂区域的面上。 第二重掺杂区域延伸到第二深度并且至少部分地在第一轻掺杂区域内。 第一隔离区域（304）形成在面上，邻接第一和第二重掺杂区域中的至少一个。 第一隔离区延伸到大于第一和第二深度中的任一个的第三深度。

公开(公告)号：US5986867A

公开(公告)日：1999-11-16

申请号：US120992

申请日：1998-07-22

申请人： Charvaka Duvvury ,  Michael D. Chaine

发明人： Charvaka Duvvury ,  Michael D. Chaine

IPC分类号： G11C11/409 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/04 ,  H01L27/108 ,  H02H9/04 ,  H03K19/003 ,  H03K19/0175 ,  H02H3/22

CPC分类号： H01L27/10805 ,  H01L27/0251 ,  H01L27/0266 ,  H02H9/046

摘要： A DRAM output protection circuit (100). A dummy NMOS transistor (116) is connected in parallel with the NMOS output transistor (102). The gate of the dummy transistor (116) is connected through a resistor (122) to ground (108). The resistor 122 value and the gate capacitance (121,127) of the dummy transistor (116) are adjusted to achieve the desired gate matching between the dummy transistor gate (120) and the NMOS output transistor gate (110).

摘要翻译： DRAM输出保护电路（100）。 虚设NMOS晶体管（116）与NMOS输出晶体管（102）并联连接。 虚拟晶体管（116）的栅极通过电阻（122）连接到地（108）。 调整虚拟晶体管（116）的电阻器122值和栅极电容（121,127）以实现虚拟晶体管栅极（120）和NMOS输出晶体管栅极（110）之间的期望的栅极匹配。

公开(公告)号：US07160795B2

公开(公告)日：2007-01-09

申请号：US10293789

申请日：2002-11-12

申请人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

发明人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01061 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

摘要翻译： 描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。 在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。

公开(公告)号：US06534833B1

公开(公告)日：2003-03-18

申请号：US09040763

申请日：1998-03-18

申请人： Charvaka Duvvury ,  Michael D. Chaine ,  Puvvada Venugopal

发明人： Charvaka Duvvury ,  Michael D. Chaine ,  Puvvada Venugopal

IPC分类号： H01L2972

CPC分类号： H01L27/0266

摘要： The invention comprises a semiconductor device with protection circuitry and a method of protecting an integrated circuit from electrostatic discharge. One aspect of the invention is a semiconductor device with protection circuitry which comprises an integrated circuit having at least one bond pad. A protection circuit is electrically connected to the bond pad and is operable to prevent damage to the integrated circuit during an electrostatic discharge event. The protection circuit comprises a first MOSFET having a first gate electrode connected in series with a second MOSFET having a second gate electrode wherein the first gate electrode and second gate electrode are commonly controlled in response to an electrostatic discharge event.

摘要翻译： 本发明包括具有保护电路的半导体器件和保护集成电路免受静电放电的方法。 本发明的一个方面是具有保护电路的半导体器件，其包括具有至少一个接合焊盘的集成电路。 保护电路电连接到接合焊盘，并且可操作以防止在静电放电事件期间对集成电路的损坏。 保护电路包括第一MOSFET，其具有与具有第二栅电极的第二MOSFET串联连接的第一栅电极，其中第一栅极电极和第二栅极电极响应于静电放电事件共同控制。