公开(公告)号：US12067484B2

公开(公告)日：2024-08-20

申请号：US16449264

申请日：2019-06-21

Applicant: Xilinx, Inc.

Inventor： Yaman Umuroglu ,  Nicholas Fraser ,  Michaela Blott ,  Kristof Denolf ,  Kornelis A. Vissers

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084

CPC classification number: G06N3/08 ,  G06N3/063 ,  G06N3/082 ,  G06N3/084

Abstract: An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.

公开(公告)号：US10523596B1

公开(公告)日：2019-12-31

申请号：US14616587

申请日：2015-02-06

Applicant: Xilinx, Inc.

Inventor： Max Ferger ,  Michaela Blott

IPC: H04L12/935

Abstract: A circuit for merging streams of data to generate sorted output data is described. The circuit comprises a first input coupled to receive a first data stream having a first set of N values; a second input coupled to receive a second data stream having second set of N values; a routing circuit coupled to the first input and the second input, the routing circuit enabling the routing of the first set of N values of the first data stream and the second set of N values of the second data stream; and a comparator circuit coupled to receive each value of the first set of N values and the second set of N values from the routing circuit, the comparator circuit having N comparators, wherein each comparator of the N comparators is coupled to receive a value of the first set of N values and a value of the second set of N values. A method of merging streams of data is also disclosed.

公开(公告)号：US10482129B1

公开(公告)日：2019-11-19

申请号：US15484455

申请日：2017-04-11

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Daniel Ziener ,  Kimon Karras

IPC: G06F7/02 ,  G06F16/00 ,  G06F16/9038 ,  G06F3/06 ,  G06F16/93 ,  G06F16/901 ,  G06F16/903

Abstract: Disclosed approaches for accessing data involve determining in a first stage of a pipelined processing circuit, hash values from keys in a data access request and determining in a second stage of the pipelined processing circuit and from a hash table, addresses associated with the hash values. In a third stage of the pipelined processing circuit, data are read at the addresses in a memory arrangement, and in a fourth stage of the pipelined processing circuit a subset of the data read from the memory arrangement is selected according to a query in the data access request. In a fifth stage of the pipelined processing circuit, the subset of the data read from the memory arrangement is merged into response data.

公开(公告)号：US10089577B2

公开(公告)日：2018-10-02

申请号：US15230164

申请日：2016-08-05

Applicant: Xilinx, Inc.

Inventor： Yaman Umuroglu ,  Michaela Blott

IPC: G06N3/08 ,  G06N3/04

Abstract: In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.

公开(公告)号：US09711194B2

公开(公告)日：2017-07-18

申请号：US14607978

申请日：2015-01-28

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

IPC: G06F12/02 ,  G06F12/08 ,  G11C7/10 ,  G06F12/0813 ,  G06F13/16

CPC classification number: G11C7/1057 ,  G06F12/0246 ,  G06F12/0813 ,  G06F13/1694 ,  G06F2212/7203 ,  G11C7/1072

Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.

公开(公告)号：US09503093B2

公开(公告)日：2016-11-22

申请号：US14260580

申请日：2014-04-24

Applicant: Xilinx, Inc.

Inventor： Kimon Karras ,  Michaela Blott ,  Kornelis A. Vissers

IPC: G06F17/50 ,  H03K19/177

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/17724

Abstract: A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Abstract translation: 可编程IC包括多个可编程资源，耦合到多个可编程资源的多个可共享逻辑电路和虚拟化电路。 多个可编程资源包括可编程逻辑电路和可编程路由资源。 虚拟化电路被配置为管理在多个可编程资源中实现的多个用户设计之间的多个可共享逻辑电路的共享。 用户设计在可编程IC上彼此通信隔离。

公开(公告)号：US20150160862A1

公开(公告)日：2015-06-11

申请号：US14100250

申请日：2013-12-09

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Kornelis A. Vissers

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/466 ,  G06F12/00 ,  G06F13/00 ,  G06F17/30221 ,  G06F17/30312 ,  G06F17/30519

Abstract: A circuit for processing data is described. The circuit comprises an input for receiving a request for implementing a key-value store data transaction; a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated with a key-value store; and a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion.

Abstract translation: 描述用于处理数据的电路。 电路包括用于接收实现键值存储数据事务的请求的输入; 与能够访问与键值存储相关联的多个存储器件的不同存储器类型相关联的多个存储器接口; 以及存储器管理电路，其基于数据传输标准，通过多个存储器接口来控制数据的路由。