公开(公告)号：US10289093B1

公开(公告)日：2019-05-14

申请号：US15850659

申请日：2017-12-21

Applicant: Xilinx, Inc.

Inventor： Patrick Lysaght ,  Parimal Patel ,  Yun Qu ,  Graham F. Schelle

IPC: G06F7/38 ,  H03K19/173 ,  G05B19/045 ,  G05B19/042

Abstract: A system can include a finite state machine generator implemented in programmable circuitry of an integrated circuit. The finite state machine generator is parameterizable to implement different finite state machines at runtime of the integrated circuit. The system can include a processor configured to execute program code. The processor is configured to provide first parameterization data to the finite state machine generator at runtime of the integrated circuit. The first parameterization data specifies a first finite state machine and the finite state machine generator implements the first finite state machine in response to receiving the first parameterization data from the processor.

公开(公告)号：US09652410B1

公开(公告)日：2017-05-16

申请号：US14278470

申请日：2014-05-15

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Paul R. Schumacher ,  Patrick Lysaght ,  Yi-Hua Yang ,  Anthony Brandon

IPC: G06F9/44 ,  H03K19/177 ,  G06F13/10

CPC classification number: G06F13/10 ,  G06F9/44 ,  H03K19/17756

Abstract: Automated modification of configuration settings for an IC (IC) includes receiving, within a data processing system, desired data for a configuration setting of an IC, reading stored data for the configuration setting. A determination is made using the data processing system that the configuration setting is static and that the stored data differs from the desired data. Responsive to the determination, configuration data including the desired data is provided from the data processing system to the IC. At least a portion of a boot process of the IC is automatically initiated, wherein the boot process uses the configuration data.

公开(公告)号：US10282326B1

公开(公告)日：2019-05-07

申请号：US14527659

申请日：2014-10-29

Applicant: Xilinx, Inc.

Inventor： Yi-Hua E. Yang ,  Patrick Lysaght ,  Austin H. Lesea ,  Graham F. Schelle ,  Paul R. Schumacher

IPC: G06F13/24 ,  G06F13/26

Abstract: An integrated circuit is provided for obtaining interrupt performance metrics. The integrated circuit includes a microprocessor executing an interrupt service routing monitoring framework that includes an interrupt handler and an application programming interface. The interrupt handler executes in response to a trigger condition and obtains timing data that includes at least one sample of a value of a timing logic according to a sampling schedule. The API exposes interrupt configuration functionality for registering the interrupt handler with a supervisory program and for configuring the interrupt handler to obtain the timing data.

公开(公告)号：US09983971B1

公开(公告)日：2018-05-29

申请号：US14713814

申请日：2015-05-15

Applicant: Xilinx, Inc.

Inventor： Yi-Hua E. Yang ,  Patrick Lysaght

IPC: G21C17/00 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3428

Abstract: Techniques for efficient benchmarking. One method includes obtaining convergent results by performing a benchmarking test with a particular length to obtain a result (time), scaling the time exponentially, performing additional benchmarking tests, obtaining results for those tests, and determining whether the results scale linearly with length. Another method includes obtaining variance for non-convergent results by performing multiple sequences of benchmarking test. Within each new sequence performed, the benchmarking tests are spaced out further apart in time. If new maximum or minimum results are obtained, then further test sequences are performed and if no new maximum or minimum results are obtained after a threshold number of sequences, then the test ends. A device and computer-readable medium for performing benchmarking are also provided herein.

公开(公告)号：US09665683B1

公开(公告)日：2017-05-30

申请号：US14921674

申请日：2015-10-23

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Patrick Lysaght

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5054

Abstract: An example method of implementing a system design for a programmable system-on-chip (SOC) having a processing system and programmable logic includes receiving a description of performance objectives for the system design. The method further includes accessing a characterization database that relates parameter settings of the processing system to performance under different traffic profiles as generated by an emulation system comprising the processing system and one or more circuit blocks implemented in the programmable logic. The method further includes obtaining a parameter set from the characterization database based on the description of the performance objectives. The method further includes generating a parameter image for setting registers of the processing system based on the parameter set.

公开(公告)号：US09581643B1

公开(公告)日：2017-02-28

申请号：US14924131

申请日：2015-10-27

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Yi-Hua E. Yang ,  Paul R. Schumacher ,  Patrick Lysaght

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G06F17/5022

Abstract: Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial design to form a test circuit design. The traffic generator circuit is configured to provide to the set of ports respective input data signals having a pattern consistent with master-to-slave communication. Operation of a test circuit design is modeled. A set of data signals generated by the circuit modules during the modeled operation of the test circuit design is captured and stored.

Abstract translation: 公开了用于测试部分电路设计的方法和电路，其包括具有一组端口的电路模块，该端口被配置为由来自部分电路省略的一个或多个电路的端口的信号驱动。 通过识别端口不被网络连接到电路设计中的另一个端口或输入/输出（I / O）引脚，并在电路模块中形成输入到从电路的端口。 交通发电机电路被添加到部分设计中以形成测试电路设计。 业务发生器电路被配置为向该组端口提供具有与主从通信一致的模式的相应输入数据信号。 测试电路设计的运行被建模。 捕获并存储在测试电路设计的建模操作期间由电路模块产生的一组数据信号。

公开(公告)号：US09529946B1

公开(公告)日：2016-12-27

申请号：US13676035

申请日：2012-11-13

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Patrick Lysaght ,  Alan M. Frost

IPC: G06F17/50 ,  G06F11/26

CPC classification number: G06F17/5022 ,  G06F11/00 ,  G06F11/261 ,  G06F11/3062 ,  G06F11/3457 ,  G06F17/5027

Abstract: An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.

Abstract translation: 集成电路可以包括可操作以执行程序代码和知识产权（IP）建模块的处理器。 IP建模块可以包括第一端口，IP建模块通过该第一端口接收第一建模数据，以及耦合到处理器的第二端口，第一IP建模块在仿真期间与处理器通信。 第一个IP建模块还可以包括一个电源仿真电路。 功率仿真电路被配置为消耗由经由第一端口接收的第一建模数据指定的可变量的功率。