公开(公告)号：US20080032486A1

公开(公告)日：2008-02-07

申请号：US11868143

申请日：2007-10-05

申请人： Toshiaki Iwamatsu ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Shigenobu Maeda

IPC分类号： H01L21/30

CPC分类号： H01L21/76243 ,  H01L21/02027 ,  H01L21/67092 ,  H01L21/68 ,  H01L21/76254 ,  H01L21/76256 ,  H01L23/544 ,  H01L29/045 ,  H01L29/78606 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer manufacturing method comprising the steps of preparing a first semiconductor wafer having a plurality of cuts formed at edge portions in crystal directions, preparing a second semiconductor wafer having a cut formed at an edge portion in a crystal direction that is different from the crystal direction of one of said plurality of cuts of said first semiconductor wafer, bonding said first and second semiconductor wafers to each other while using said one of said plurality of cuts of said first semiconductor wafer and said cut of said second semiconductor wafer in order to position said first and second semiconductor wafers, with another one of said plurality of cuts of said first semiconductor wafer being engaged with a guide portion of a semiconductor wafer manufacturing apparatus, thinning said first semiconductor wafer, implanting oxygen ions from said first semiconductor wafer side into a neighborhood of a part where said first and second semiconductor wafers are bonded to each other, and forming the portion implanted with the oxygen ions into an oxide film layer by a thermal treatment.

摘要翻译： 一种半导体晶片制造方法，包括以下步骤：制备在晶体方向上形成有多个切口的第一半导体晶片，所述第一半导体晶片具有在晶体方向上不同晶体的边缘部分处形成的切口的第二半导体晶片 所述第一半导体晶片的所述多个切口中的一个切口的方向，将所述第一和第二半导体晶片彼此接合，同时使用所述第一半导体晶片的所述多个切口和所述第二半导体晶片的所述切口中的所述一个切口以便定位 所述第一和第二半导体晶片，所述第一半导体晶片的所述多个切口中的另一个与半导体晶片制造设备的引导部分接合，使所述第一半导体晶片变薄，将氧离子从所述第一半导体晶片侧注入到 所述第一和第二半导体晶片的部分附近 e彼此键合，并且通过热处理将注入氧离子的部分形成氧化物膜层。

公开(公告)号：US07321152B2

公开(公告)日：2008-01-22

申请号：US11498800

申请日：2006-08-04

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

IPC分类号： H01L29/76 ,  H01L31/113

CPC分类号： H01L29/78609 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78639

摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same.A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

摘要翻译： 提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。 漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。 漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。 定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

公开(公告)号：US07297585B2

公开(公告)日：2007-11-20

申请号：US11493529

申请日：2006-07-27

申请人： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L21/8238

CPC分类号： H01L29/78615 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

公开(公告)号：US07291542B2

公开(公告)日：2007-11-06

申请号：US11223970

申请日：2005-09-13

申请人： Toshiaki Iwamatsu ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Shigenobu Maeda

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76243 ,  H01L21/02027 ,  H01L21/67092 ,  H01L21/68 ,  H01L21/76254 ,  H01L21/76256 ,  H01L23/544 ,  H01L29/045 ,  H01L29/78606 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a crystal direction notch (32a) and a crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers. Thus an MOS transistor with a sufficiently improved current driving capability can be fabricated on the semiconductor wafer with the two wafers positioned in crystal directions shifted from each other.

摘要翻译： 提供一种可以充分提高MOS晶体管的电流驱动能力的半导体晶片及其制造方法。 其中形成SOI层（32）的SOI层晶片具有<100>晶向切口（32a）和<110>晶体方向凹口（32b）。 SOI层晶片和支撑基板晶片（1）彼此接合，使得支撑基板晶片（1）的凹口（23a）和（110）晶体方向缺口（1a）与 彼此。 当通过使用凹口（32a）和凹口（1a）将两个晶片接合以定位两个晶片时，SOI层晶片的另一个凹口（32b）可以与半导体晶片制造的引导构件接合 用于防止由于晶片之间的相对转动引起的定位误差的装置。 因此，可以在半导体晶片上制造具有充分改善的电流驱动能力的MOS晶体管，其中两个晶片位于晶体方向彼此偏移。

公开(公告)号：US20070132028A1

公开(公告)日：2007-06-14

申请号：US11677951

申请日：2007-02-22

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

公开(公告)号：US20070108494A1

公开(公告)日：2007-05-17

申请号：US11621177

申请日：2007-01-09

申请人： Shigenobu Maeda ,  Hiroyuki Takashino ,  Toshihide Oka

发明人： Shigenobu Maeda ,  Hiroyuki Takashino ,  Toshihide Oka

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L21/26586 ,  H01L21/74 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0808 ,  H01L27/0811 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/94

摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.

摘要翻译： 本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。 形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜 分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。 另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不 具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

公开(公告)号：US07176515B2

公开(公告)日：2007-02-13

申请号：US11220583

申请日：2005-09-08

申请人： Shigenobu Maeda ,  Hiroyuki Takashino ,  Toshihide Oka

发明人： Shigenobu Maeda ,  Hiroyuki Takashino ,  Toshihide Oka

IPC分类号： H01L29/94

CPC分类号： H01L21/26586 ,  H01L21/74 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0808 ,  H01L27/0811 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/94

摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.

摘要翻译： 本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。 形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜 分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。 另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不 具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

公开(公告)号：US20070032001A1

公开(公告)日：2007-02-08

申请号：US11543213

申请日：2006-10-05

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / SUP> / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

公开(公告)号：US20070007595A1

公开(公告)日：2007-01-11

申请号：US11520640

申请日：2006-09-14

申请人： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

发明人： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

IPC分类号： H01L27/12

CPC分类号： H01L23/481 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

摘要翻译： 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T 1）。 布线（17a）通过接触插塞（15A）与晶体管（T 1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，所述背金属（18）通过散热塞（16）与布线（17a）连接。 接触塞（15A），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比 氧化硅膜（11）和支撑基板（10）。

公开(公告)号：US07144764B2

公开(公告)日：2006-12-05

申请号：US10949451

申请日：2004-09-27

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L21/762

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

摘要翻译： 本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。 在图案化氮化膜（22）之后，测量SOI层3的厚度（S 2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S 3） 。 为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。 使用所确定的蚀刻条件，并且通过使用图案化的氮化物膜22作为蚀刻掩模形成沟槽TR 2（S 4）。