公开(公告)号：US20050010897A1

公开(公告)日：2005-01-13

申请号：US10880523

申请日：2004-07-01

申请人： Hajime Ogawa ,  Taketo Heishi ,  Shuichi Takayama ,  Chen Zhao

发明人： Hajime Ogawa ,  Taketo Heishi ,  Shuichi Takayama ,  Chen Zhao

IPC分类号： G06F11/28 ,  G06F9/44

CPC分类号： G06F8/30 ,  G06F8/43 ,  G06F8/51

摘要： A test program generating apparatus for a compiler comprising: a conditional expression generating unit operable to receive a description of a control structure of a program and generate a plurality of conditional expressions to be inserted into insert parts of the conditional expressions of the control structure using a linear programming method, the plurality of conditional expressions allowing a control flow of the program to pass through all paths in the control structure; an initial value generating unit operable to generate initial values of variables, for each of all the paths, which are included in the plurality of conditional expressions for allowing the control flow of the program to pass through all the paths in the control structure; and a test program generating unit operable to generate a test program based on the control structure, the conditional expressions and the initial values.

摘要翻译： 一种用于编译器的测试程序生成装置，包括：条件表达式生成单元，用于接收对程序的控制结构的描述，并生成多个条件表达式，以使用以下操作插入到控制结构的条件表达式的插入部分中 所述多个条件表达式允许所述程序的控制流程通过所述控制结构中的所有路径; 初始值生成单元，用于针对包含在所述多个条件表达式中的每个所述路径生成用于允许所述程序的控制流通过所述控制结构中的所有路径的变量的初始值; 以及测试程序生成单元，其可操作以基于所述控制结构，所述条件表达式和所述初始值生成测试程序。

公开(公告)号：US09651939B2

公开(公告)日：2017-05-16

申请号：US13608111

申请日：2012-09-10

申请人： Junichi Tezuka ,  Hajime Ogawa

发明人： Junichi Tezuka ,  Hajime Ogawa

IPC分类号： G05B15/00 ,  G05B19/4068 ,  G05B19/408

CPC分类号： G05B19/4068 ,  G05B19/408

摘要： A numerical controller having a display function for comparing data at a predetermined position regardless of a change in a processing condition. The numerical controller comprises a numerical controlling part which controls each drive axis based on a predetermined position command; a position data obtaining part which obtains position data of each axis and a tool representative point of the machine tool; a movement distance calculating part which calculates movement distance of the axis and the tool representative point based on the obtained position data and dimensional information of each component of the machine tool; a physical data obtaining part which obtains physical data of each axis and the tool; a data converting part which converts the obtained time axis-based physical data into movement distance-based data; a distance-based data storing part which stores the movement distance-based data; and a displaying part which displays the movement distance-based data.

公开(公告)号：US08812142B2

公开(公告)日：2014-08-19

申请号：US13494079

申请日：2012-06-12

申请人： Junichi Tezuka ,  Hajime Ogawa

发明人： Junichi Tezuka ,  Hajime Ogawa

IPC分类号： G06F17/00

CPC分类号： G05B19/408 ,  G05B2219/23181 ,  G05B2219/40162

摘要： A numerical controller, wherein an operator, even remotely, can recognize a sound of a machine tool or the like, and can intuitively know the effect in adjusting the parameter. The numerical controller includes a drive axis controlling part configured to control a drive axis; a drive axis data storing part configured to obtain a physical quantity of the drive axis as time-series data and store the time-series data; a displaying part configured to convert the time-series data into a predetermined indication form and display the data as at least one displayed waveform; a selecting part configured to select the displayed waveform by input operation of the operator; a sound converting part configured to convert the selected waveform into sound conversion data, a type of which is capable of being output as sound; and a sound outputting part configured to output the generated sound conversion data as sound.

摘要翻译： 数值控制器，其中操作者甚至远程地可以识别机床的声音等，并且可以直观地知道调整参数的效果。 数值控制器包括构造成控制驱动轴的驱动轴控制部分; 驱动轴数据存储部，被配置为获取所述驱动轴的物理量作为时间序列数据，并存储所述时间序列数据; 显示部，被配置为将所述时间序列数据转换成预定的指示形式，并将所述数据显示为至少一个显示的波形; 配置为通过操作者的输入操作选择所显示的波形的选择部; 声音转换部，被配置为将所选择的波形转换为声音转换数据，其类型能够作为声音输出; 以及声音输出部，被配置为将所生成的声音转换数据输出为声音。

公开(公告)号：US20130076287A1

公开(公告)日：2013-03-28

申请号：US13564989

申请日：2012-08-02

申请人： Yasusuke Iwashita ,  Hajime Ogawa

发明人： Yasusuke Iwashita ,  Hajime Ogawa

IPC分类号： G05B13/02

CPC分类号： G05B19/4068 ,  G05B2219/35349

摘要： A numerical controller capable of visually and accurately analyzing a change of the tool trajectory before and after changing a processing condition, whereby a parameter of a drive axis can be properly adjusted. The numerical controller comprises a numeric controlling part which controls each drive axis based on a predetermined position command; a position data obtaining part which obtains position data of each drive axis controlled by the numerical controlling part; a tool coordinate calculating part which calculates a coordinate of a tool center point based on position feedback or obtained position data of each drive axis and information of a mechanical structure of a machine tool; a tool trajectory storing part which stores the calculated coordinate of the tool center point as a feedback trajectory; and a displaying part which displays the stored feedback trajectory on a display.

摘要翻译： 一种数字控制器，其能够在改变处理条件之前和之后视觉上和精确地分析工具轨迹的变化，从而可以适当地调整驱动轴的参数。 数值控制器包括：数字控制部，其基于预定位置指令控制各驱动轴; 位置数据获取部，其获取由所述数值控制部控制的各驱动轴的位置数据; 工具坐标计算部，其基于位置反馈或所获得的各驱动轴的位置数据和机床的机械结构的信息来计算刀具中心点的坐标; 工具轨迹存储部，其将所计算的所述工具中心点的坐标存储为反馈轨迹; 以及在显示器上显示存储的反馈轨迹的显示部分。

公开(公告)号：US07823142B2

公开(公告)日：2010-10-26

申请号：US11245357

申请日：2005-10-07

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/45

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a至409c解码分支指令时，分支指令中包括的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US07698696B2

公开(公告)日：2010-04-13

申请号：US10608040

申请日：2003-06-30

申请人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

发明人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/443

摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

摘要翻译： 编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元， 根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理 指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

公开(公告)号：US07571432B2

公开(公告)日：2009-08-04

申请号：US10944831

申请日：2004-09-21

申请人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

发明人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

摘要翻译： 编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。 该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。 上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

公开(公告)号：US07380112B2

公开(公告)日：2008-05-27

申请号：US10805381

申请日：2004-03-22

申请人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

发明人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30072 ,  G06F8/447 ,  G06F9/325

摘要： The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

摘要翻译： 本发明提供了一种具有小规模电路并且能够在消耗少量功率的同时高速执行循环处理的处理器。 当处理器解码指​​令“jloop C 6，C 1：C 4，TAR，Ra”时，当寄存器Ra的值小于0时，处理器（i）将条件标志C 4设置为0，（ii） 将条件标志C 2的值移动到条件标志C1，将条件标志C 3的值移动到条件标志C 2，并将条件标志C 4的值移动到条件标志C 3和C 6，（iii）向寄存器Ra添加-1，并将结果存储到寄存器Ra中，（iv）分支到由分支寄存器（TAR）指定的地址。 当没有填充分支目标指令时，跳转缓冲区将用分支目标指令填充。

公开(公告)号：US20080046688A1

公开(公告)日：2008-02-21

申请号：US11896369

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F15/80 ,  G06F9/315

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件 当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。 然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

公开(公告)号：US07281117B2

公开(公告)日：2007-10-09

申请号：US10668358

申请日：2003-09-24

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302 ,  G06F9/318

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件 当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。 然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。