公开(公告)号：US08536890B2

公开(公告)日：2013-09-17

申请号：US12865201

申请日：2009-02-05

申请人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

发明人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

IPC分类号： G01R31/20

CPC分类号： G01R31/303 ,  G01R31/2889 ,  G01R31/3025

摘要： A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.

摘要翻译： 半导体检查装置包括用于向其中形成有一个或多个对象芯片的半导体晶片发送信号或电源的探针卡，并且构成为使得第一半导体晶片面向探针卡的第一面，并且使得第二半导体 晶片面对第一面的相对侧的探针卡的第二面。 探针卡包括一个或多个检查芯片，其可以执行与第一半导体晶片中的第一对象芯片和第二半导体晶片中的第二对象芯片的非接触传输。

公开(公告)号：US08570056B2

公开(公告)日：2013-10-29

申请号：US12866223

申请日：2009-02-26

申请人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

发明人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

IPC分类号： G01R31/00 ,  G01R31/02

CPC分类号： G01R31/2891

摘要： A semiconductor inspection apparatus comprising: a plurality of wafer stages, provided independently for each of a plurality of laminated semiconductor wafers, that directly or indirectly secure the corresponding semiconductor wafers and that possess a mechanism for positioning the corresponding semiconductor wafers; and a probe card, arranged outside or in between the plurality of laminated semiconductor wafers so as to face the semiconductor wafers, that transmits a signal or power to the plurality of semiconductor wafers.

摘要翻译： 一种半导体检查装置，包括：对于多个层叠半导体晶片中的每一个独立设置的多个晶片台，其直接或间接固定相应的半导体晶片，并且具有用于定位相应的半导体晶片的机构; 以及探针卡，其布置在多个层叠半导体晶片之间或之间，以面对半导体晶片，其向多个半导体晶片发送信号或电力。

公开(公告)号：US5598105A

公开(公告)日：1997-01-28

申请号：US562746

申请日：1995-11-27

申请人： Itaru Kurosawa ,  Hiroshi Nakagawa ,  Masahiro Aoyagi ,  Masaaki Maezawa ,  Takashi Nanya ,  Yoshio Kameda

发明人： Itaru Kurosawa ,  Hiroshi Nakagawa ,  Masahiro Aoyagi ,  Masaaki Maezawa ,  Takashi Nanya ,  Yoshio Kameda

IPC分类号： H01L39/22 ,  H03K19/195

CPC分类号： H03K19/1954

摘要： An elementary cell uses single-flux-quanta as two-valued logic propagation signals and is effective for Constructing asynchronous superconducting logic circuits. The elementary cell comprises one OR circuit section and one AND circuit section. Input pulses applied to two input terminals of the elementary cell are split at signal splitting sections in the elementary cell and applied to both inputs of the OR circuit section and both inputs of the AND circuit section. The output of the OR circuit section is defined as the OR output of the elementary cell. A first arrival pulse memory section is provided in the AND circuit section and when one of two input pulses input to the two input terminals of the AND circuit section arrives before the other, this fact is recorded in the first arrival pulse memory section as logical "1". When the other input pulse arrives while logical "1" is recorded in the first arrival pulse memory section, the AND circuit section produces an AND output which is defined as the AND output of the elementary cell. When a reset signal pulse is applied to a reset terminal, the first arrival pulse memory section is reset.

摘要翻译： 基本单元使用单通量量子作为二值逻辑传播信号，对于构造异步超导逻辑电路是有效的。 基本单元包括一个OR电路部分和一个AND电路部分。 施加到基本单元的两个输入端子的输入脉冲在基本单元中的信号分离部分处被分离，并且被施加到“或”电路部分的两个输入端和“与”电路部分的两个输入端。 OR电路部分的输出被定义为基本单元的OR输出。 在AND电路部分中设置第一到达脉冲存储器部分，并且当输入到AND电路部分的两个输入端子的两个输入脉冲之一到达另一个时，该事实被记录在第一到达脉冲存储器部分中作为逻辑“ 1“。 当在第一到达脉冲存储器部分中记录逻辑“1”时另一个输入脉冲到达时，与电路部分产生被定义为基本单元的与输出的“与”输出。 当将复位信号脉冲施加到复位端子时，第一到达脉冲存储器部分被复位。

公开(公告)号：US20100321054A1

公开(公告)日：2010-12-23

申请号：US12865201

申请日：2009-02-05

申请人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

发明人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

IPC分类号： G01R31/20 ,  G01R31/26

CPC分类号： G01R31/303 ,  G01R31/2889 ,  G01R31/3025

摘要： A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.

摘要翻译： 半导体检查装置包括用于向其中形成有一个或多个对象芯片的半导体晶片发送信号或电源的探针卡，并且构成为使得第一半导体晶片面向探针卡的第一面，并且使得第二半导体 晶片面对第一面的相对侧的探针卡的第二面。 探针卡包括一个或多个检查芯片，其可以执行与第一半导体晶片中的第一对象芯片和第二半导体晶片中的第二对象芯片的非接触传输。

公开(公告)号：US06703857B2

公开(公告)日：2004-03-09

申请号：US10201965

申请日：2002-07-25

申请人： Yoshio Kameda ,  Shinichi Yorozu

发明人： Yoshio Kameda ,  Shinichi Yorozu

IPC分类号： H03K19195

CPC分类号： H03K19/1954

摘要： An integrated circuit comprises plural superconducting circuit blocks connected through superconducting wiring strips, and each superconducting circuit block includes at least one superconducting logic circuit, constant input/output circuits connected between the input/output nodes of the circuit block and the superconducting logic circuit; parameters of the constant input/output circuits are regulated such that statically flow-in/flow-out current is approximately equal to zero at the input/output nodes of the superconducting logic circuit, whereby the superconducting logic circuit operates at the optimum operating point after the integration.

摘要翻译： 集成电路包括通过超导布线条连接的多个超导电路块，每个超导电路块包括至少一个超导逻辑电路，连接在电路块的输入/输出节点与超导逻辑电路之间的恒定输入/输出电路; 调节恒定输入/输出电路的参数，使得在超导逻辑电路的输入/输出节点处静态流入/流出电流近似等于零，由此超导逻辑电路在最佳工作点之后运行 整合。

公开(公告)号：US20120307650A1

公开(公告)日：2012-12-06

申请号：US13577412

申请日：2010-12-21

申请人： Yoshio Kameda ,  Hideaki Saito

发明人： Yoshio Kameda ,  Hideaki Saito

IPC分类号： H04L12/26

CPC分类号： G06F11/0751 ,  G06F11/183 ,  G06F11/184

摘要： At least one of components of a multiplex system can detect a failure by itself. An output of the multiplex system is determined from outputs of the components and a failure detection notification. Thus, a multiplex system having higher reliability is provided. A multiplex system 1 includes a plurality of components including a component A1 (10a), a component B1 (10b), and a component C1 (10c) that cannot detect a failure by itself and a component A2 (20a) and a component B2 (20b) that can detect a failure by itself. Outputs 11a, 11b, 11c, 21a, and 21b of the components and failure detection notifications 22a and 22b are inputted to an output determination part 30. The output determination part 30 determines an output of the multiplex system 1 from the outputs of the components and the failure detection notifications.

摘要翻译： 多路复用系统的至少一个组件可以自己检测故障。 多路复用系统的输出是由组件的输出和故障检测通知确定的。 因此，提供了具有更高可靠性的多路复用系统。 复用系统1包括多个组件，包括组件A1（10a），组件B1（10b）和组件C1（10c），组件C1（10c）本身不能检测到故障和组件A2（20a）和组件B2（ 20b），可以自己检测故障。 部件的输出11a，11b，11c，21a，21b和故障检测通知22a，22b被输入到输出判断部30.输出判断部30根据部件的输出，判定多路复用系统1的输出， 故障检测通知。