公开(公告)号：US20120307650A1

公开(公告)日：2012-12-06

申请号：US13577412

申请日：2010-12-21

申请人： Yoshio Kameda ,  Hideaki Saito

发明人： Yoshio Kameda ,  Hideaki Saito

IPC分类号： H04L12/26

CPC分类号： G06F11/0751 ,  G06F11/183 ,  G06F11/184

摘要： At least one of components of a multiplex system can detect a failure by itself. An output of the multiplex system is determined from outputs of the components and a failure detection notification. Thus, a multiplex system having higher reliability is provided. A multiplex system 1 includes a plurality of components including a component A1 (10a), a component B1 (10b), and a component C1 (10c) that cannot detect a failure by itself and a component A2 (20a) and a component B2 (20b) that can detect a failure by itself. Outputs 11a, 11b, 11c, 21a, and 21b of the components and failure detection notifications 22a and 22b are inputted to an output determination part 30. The output determination part 30 determines an output of the multiplex system 1 from the outputs of the components and the failure detection notifications.

摘要翻译： 多路复用系统的至少一个组件可以自己检测故障。 多路复用系统的输出是由组件的输出和故障检测通知确定的。 因此，提供了具有更高可靠性的多路复用系统。 复用系统1包括多个组件，包括组件A1（10a），组件B1（10b）和组件C1（10c），组件C1（10c）本身不能检测到故障和组件A2（20a）和组件B2（ 20b），可以自己检测故障。 部件的输出11a，11b，11c，21a，21b和故障检测通知22a，22b被输入到输出判断部30.输出判断部30根据部件的输出，判定多路复用系统1的输出， 故障检测通知。

公开(公告)号：US08536890B2

公开(公告)日：2013-09-17

申请号：US12865201

申请日：2009-02-05

申请人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

发明人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

IPC分类号： G01R31/20

CPC分类号： G01R31/303 ,  G01R31/2889 ,  G01R31/3025

摘要： A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.

摘要翻译： 半导体检查装置包括用于向其中形成有一个或多个对象芯片的半导体晶片发送信号或电源的探针卡，并且构成为使得第一半导体晶片面向探针卡的第一面，并且使得第二半导体 晶片面对第一面的相对侧的探针卡的第二面。 探针卡包括一个或多个检查芯片，其可以执行与第一半导体晶片中的第一对象芯片和第二半导体晶片中的第二对象芯片的非接触传输。

公开(公告)号：US08399960B2

公开(公告)日：2013-03-19

申请号：US12920381

申请日：2009-02-20

申请人： Yoshihiro Nakagawa ,  Koichiro Noguchi ,  Yoshio Kameda ,  Masayuki Mizuno

发明人： Yoshihiro Nakagawa ,  Koichiro Noguchi ,  Yoshio Kameda ,  Masayuki Mizuno

IPC分类号： H01L27/08

CPC分类号： H01L27/0688 ,  H01L23/48 ,  H01L23/5227 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A plurality of semiconductor chips are juxtaposed, each having an electromagnetic induction coil disposed thereon. A signal is transmitted by way of electromagnetic induction between the electromagnetic induction coils disposed on a pair of adjacent semiconductor chips.

摘要翻译： 多个半导体芯片并置，每个具有布置在其上的电磁感应线圈。 在布置在一对相邻半导体芯片上的电磁感应线圈之间通过电磁感应传输信号。

公开(公告)号：US20110006443A1

公开(公告)日：2011-01-13

申请号：US12920452

申请日：2009-02-19

申请人： Koichiro Noguchi ,  Yoshio Kameda ,  Yoshihiro Nakagawa ,  Masayuki Mizuno

发明人： Koichiro Noguchi ,  Yoshio Kameda ,  Yoshihiro Nakagawa ,  Masayuki Mizuno

IPC分类号： H01L23/48

CPC分类号： H01L23/645 ,  H01L23/5227 ,  H01L23/585 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/08 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06596

摘要： Disclosed is a semiconductor device composed of a plurality of semiconductor integrated circuits and a plurality of coils. During the production process of the semiconductor device, the plurality of coils are so arranged that the coil surfaces are generally perpendicular to the front surface of a chip of the semiconductor integrated circuits wherein metal films are laminated. A signal is transmitted between a pair of adjacent coils among the plurality of coils.

摘要翻译： 公开了由多个半导体集成电路和多个线圈组成的半导体器件。 在半导体器件的生产过程中，多个线圈被布置成使得线圈表面大致垂直于半导体集成电路的芯片的前表面，其中金属膜被层压。 信号在多个线圈中的一对相邻线圈之间传输。

公开(公告)号：US08570056B2

公开(公告)日：2013-10-29

申请号：US12866223

申请日：2009-02-26

申请人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

发明人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

IPC分类号： G01R31/00 ,  G01R31/02

CPC分类号： G01R31/2891

摘要： A semiconductor inspection apparatus comprising: a plurality of wafer stages, provided independently for each of a plurality of laminated semiconductor wafers, that directly or indirectly secure the corresponding semiconductor wafers and that possess a mechanism for positioning the corresponding semiconductor wafers; and a probe card, arranged outside or in between the plurality of laminated semiconductor wafers so as to face the semiconductor wafers, that transmits a signal or power to the plurality of semiconductor wafers.

摘要翻译： 一种半导体检查装置，包括：对于多个层叠半导体晶片中的每一个独立设置的多个晶片台，其直接或间接固定相应的半导体晶片，并且具有用于定位相应的半导体晶片的机构; 以及探针卡，其布置在多个层叠半导体晶片之间或之间，以面对半导体晶片，其向多个半导体晶片发送信号或电力。

公开(公告)号：US20120233506A1

公开(公告)日：2012-09-13

申请号：US13510621

申请日：2010-11-26

申请人： Yoshio Kameda ,  Masayuki Mizuno

发明人： Yoshio Kameda ,  Masayuki Mizuno

IPC分类号： G06F11/28

CPC分类号： G06F11/1658 ,  G06F11/0793 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1687 ,  G06F11/2236

摘要： A redundant computing system is composed of two systems: a first arithmetic processing unit (A-system) and a second arithmetic processing unit (B-system) having the same functions. A diagnosis control unit performs diagnosis of one system while the other system is performing arithmetic processing operation. The diagnosis control unit controls the input to the first and second arithmetic processing units by way of an input control unit according to the diagnosis operation, and an output control unit controls the output from the first and second arithmetic processing units according to the diagnosis result. After termination of the diagnosis, a value is copied from a storage unit of the system which has not been diagnosed to a storage unit of the system which has been diagnosed, and the redundant computing system resumes the redundant operation.

摘要翻译： 冗余计算系统由具有相同功能的第一算术处理单元（A系统）和第二算术处理单元（B系统）组成。 诊断控制单元执行一个系统的诊断，而另一个系统执行算术处理操作。 诊断控制单元根据诊断操作通过输入控制单元控制对第一和第二算术处理单元的输入，并且输出控制单元根据诊断结果控制来自第一和第二算术处理单元的输出。 在诊断结束后，从尚未被诊断的系统的存储单元复制到被诊断的系统的存储单元，并且冗余计算系统恢复冗余操作。

公开(公告)号：US08862934B2

公开(公告)日：2014-10-14

申请号：US13510621

申请日：2010-11-26

申请人： Yoshio Kameda ,  Masayuki Mizuno

发明人： Yoshio Kameda ,  Masayuki Mizuno

IPC分类号： G06F11/00 ,  G06F11/22 ,  G06F11/07 ,  G06F11/16

CPC分类号： G06F11/1658 ,  G06F11/0793 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1687 ,  G06F11/2236

摘要： A redundant computing system is composed of two systems: a first arithmetic processing unit (A-system) and a second arithmetic processing unit (B-system) having the same functions. A diagnosis control unit performs diagnosis of one system while the other system is performing arithmetic processing operation. The diagnosis control unit controls the input to the first and second arithmetic processing units by way of an input control unit according to the diagnosis operation, and an output control unit controls the output from the first and second arithmetic processing units according to the diagnosis result. After termination of the diagnosis, a value is copied from a storage unit of the system which has not been diagnosed to a storage unit of the system which has been diagnosed, and the redundant computing system resumes the redundant operation.

摘要翻译： 冗余计算系统由具有相同功能的第一算术处理单元（A系统）和第二算术处理单元（B系统）组成。 诊断控制单元执行一个系统的诊断，而另一个系统执行算术处理操作。 诊断控制单元根据诊断操作通过输入控制单元控制对第一和第二算术处理单元的输入，并且输出控制单元根据诊断结果控制来自第一和第二算术处理单元的输出。 在诊断结束后，从尚未被诊断的系统的存储单元复制到被诊断的系统的存储单元，并且冗余计算系统恢复冗余操作。

公开(公告)号：US08441277B2

公开(公告)日：2013-05-14

申请号：US12810877

申请日：2008-12-16

申请人： Koichiro Noguchi ,  Yoshio Kameda ,  Koichi Nose ,  Masayuki Mizuno ,  Toshinobu Ono

发明人： Koichiro Noguchi ,  Yoshio Kameda ,  Koichi Nose ,  Masayuki Mizuno ,  Toshinobu Ono

IPC分类号： G01R31/26

CPC分类号： G01R31/31908

摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.

摘要翻译： 提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。 半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为 由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

公开(公告)号：US5598105A

公开(公告)日：1997-01-28

申请号：US562746

申请日：1995-11-27

申请人： Itaru Kurosawa ,  Hiroshi Nakagawa ,  Masahiro Aoyagi ,  Masaaki Maezawa ,  Takashi Nanya ,  Yoshio Kameda

发明人： Itaru Kurosawa ,  Hiroshi Nakagawa ,  Masahiro Aoyagi ,  Masaaki Maezawa ,  Takashi Nanya ,  Yoshio Kameda

IPC分类号： H01L39/22 ,  H03K19/195

CPC分类号： H03K19/1954

摘要： An elementary cell uses single-flux-quanta as two-valued logic propagation signals and is effective for Constructing asynchronous superconducting logic circuits. The elementary cell comprises one OR circuit section and one AND circuit section. Input pulses applied to two input terminals of the elementary cell are split at signal splitting sections in the elementary cell and applied to both inputs of the OR circuit section and both inputs of the AND circuit section. The output of the OR circuit section is defined as the OR output of the elementary cell. A first arrival pulse memory section is provided in the AND circuit section and when one of two input pulses input to the two input terminals of the AND circuit section arrives before the other, this fact is recorded in the first arrival pulse memory section as logical "1". When the other input pulse arrives while logical "1" is recorded in the first arrival pulse memory section, the AND circuit section produces an AND output which is defined as the AND output of the elementary cell. When a reset signal pulse is applied to a reset terminal, the first arrival pulse memory section is reset.

摘要翻译： 基本单元使用单通量量子作为二值逻辑传播信号，对于构造异步超导逻辑电路是有效的。 基本单元包括一个OR电路部分和一个AND电路部分。 施加到基本单元的两个输入端子的输入脉冲在基本单元中的信号分离部分处被分离，并且被施加到“或”电路部分的两个输入端和“与”电路部分的两个输入端。 OR电路部分的输出被定义为基本单元的OR输出。 在AND电路部分中设置第一到达脉冲存储器部分，并且当输入到AND电路部分的两个输入端子的两个输入脉冲之一到达另一个时，该事实被记录在第一到达脉冲存储器部分中作为逻辑“ 1“。 当在第一到达脉冲存储器部分中记录逻辑“1”时另一个输入脉冲到达时，与电路部分产生被定义为基本单元的与输出的“与”输出。 当将复位信号脉冲施加到复位端子时，第一到达脉冲存储器部分被复位。

公开(公告)号：US08330254B2

公开(公告)日：2012-12-11

申请号：US12647639

申请日：2009-12-28

申请人： Masayuki Furumiya ,  Hiroaki Ohkubo ,  Fuyuki Okamoto ,  Masayuki Mizuno ,  Koichi Nose ,  Yoshihiro Nakagawa ,  Yoshio Kameda

发明人： Masayuki Furumiya ,  Hiroaki Ohkubo ,  Fuyuki Okamoto ,  Masayuki Mizuno ,  Koichi Nose ,  Yoshihiro Nakagawa ,  Yoshio Kameda

IPC分类号： H01L23/544

CPC分类号： H01L23/48 ,  G01R31/2884 ,  G01R31/3025 ,  G01R31/31721 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/544 ,  H01L24/06 ,  H01L2223/5446 ,  H01L2924/01029

摘要： A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

摘要翻译： 一种半导体器件包括其半导体芯片形成区域和位于半导体芯片形成区域之间的划线区域形成的半导体晶片，设置在半导体晶片上的多个半导体芯片电路部分，设置在每个半导体芯片形成区域中的多个第一导电层 电连接到每个电路部分的半导体芯片形成区域以及跨越划线区域的一部分将第一导电层彼此电连接的第一连接部分。 外部电源或接地焊盘连接到第一导电层和第一连接部分中的任一个。 半导体器件包括连接到电路部分的通信部分，其通过电容耦合或电感耦合与外部进行通信。