公开(公告)号：US06436762B1

公开(公告)日：2002-08-20

申请号：US09855238

申请日：2001-05-14

申请人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Min-Hsiung Chiang ,  Hsiao-Hui Tseng ,  Chung-Wei Chang

发明人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Min-Hsiung Chiang ,  Hsiao-Hui Tseng ,  Chung-Wei Chang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/20

CPC分类号： H01L27/10888 ,  H01L27/10811 ,  H01L28/91

摘要： A method is described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After forming FETs for the memory cells, an interpolysilicon oxide (IPO) layer is deposited, and first and second plug contacts are formed in the IPO to the FET source/drain areas for capacitors and bit line contacts, respectively. A capacitor node oxide is deposited, and first openings are etched in which crown capacitor bottom electrodes are formed. After etching back the node oxide a thin interelectrode dielectric layer is formed and a conformal conducting layer is deposited to form capacitor top electrodes. A photoresist mask is used to etch openings in the conducting layer over the second plug contacts, and an isotropic etch is used to recess the openings under the mask to increase the spacing between the capacitor top electrodes and the bit line contacts to improve the overlay margin. The photoresist mask is removed and an interlevel dielectric (ILD) layer is deposited. Bit-line contact openings are etched in the ILD layer aligned over the recessed openings and in the node oxide to the second contact plugs. Bit-line contact plugs are formed extending through the recessed openings, and a first conducting layer is deposited and patterned to form bit lines and to complete the memory cells for the DRAM.

摘要翻译： 描述了一种用于制造具有改进的位线和电容器顶部电极之间的覆盖边缘的电容器下位线（CUB）DRAM单元的方法。 在形成用于存储单元的FET之后，沉积多晶硅氧化物（IPO）层，并且在IPO中分别将第一和第二插头触点形成到用于电容器和位线触点的FET源极/漏极区域。 沉积电容器节点氧化物，并且蚀刻第一开口，其中形成冠电容器底部电极。 在蚀刻回节点氧化物之后，形成薄的电极间电介质层，并且淀积保形导电层以形成电容器顶部电极。 使用光致抗蚀剂掩模来蚀刻导电层上的第二插头触点上的开口，并且使用各向同性蚀刻来凹陷掩模下方的开口以增加电容器顶部电极和位线触点之间的间隔，以改善覆盖边缘 。 去除光致抗蚀剂掩模并沉积层间电介质（ILD）层。 在ILD层中蚀刻位线接触开口，其在凹入的开口上以及在节点氧化物中对齐到第二接触插塞。 位线接触插塞形成为延伸穿过凹入的开口，并且第一导电层被沉积和图案化以形成位线并且完成用于DRAM的存储单元。

公开(公告)号：US06187659B1

公开(公告)日：2001-02-13

申请号：US09368861

申请日：1999-08-06

申请人： Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

发明人： Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC分类号： H01L214763

CPC分类号： H01L27/10855 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897

摘要： A new method is provided to create a gradated dopant concentration in the contact plug of DRAM devices whereby a high dopant concentration is present at the bottom of the plug and a low dopant concentration is present at the top of the plug. Two layers of dielectric are deposited; the upper layer serves as a layer to adjust the dopant concentration in the lower layer. This adjustment is done by Rapid Thermal anneal of both layers of dielectric. After the dopant concentration has been adjusted, the upper layer of dielectric is removed and the upper section of the contact node is formed using lightly doped poly. The high dopant concentration at the bottom of the contact plug results in low contact resistance between the plug and the underlying silicon substrate. A low dopant concentration at the top surface of the contact plug results in low oxidation of the surface of the plug.

摘要翻译： 提供了一种新的方法来在DRAM器件的接触插塞中产生渐变的掺杂剂浓度，由此在插塞的底部存在高的掺杂剂浓度，并且在插头的顶部存在低的掺杂剂浓度。 沉积两层电介质; 上层用作调整下层中的掺杂剂浓度的层。 这种调整是通过两层电介质的快速热退火进行的。 在调整掺杂剂浓度之后，去除电介质的上层，并且使用轻掺杂的多晶形成接触节点的上部。 接触插塞底部的高掺杂剂浓度导致插头和底层硅衬底之间的低接触电阻。 在接触塞顶表面的低掺杂剂浓度导致插塞表面的低氧化。

公开(公告)号：US06168984A

公开(公告)日：2001-01-02

申请号：US09419103

申请日：1999-10-15

申请人： Chue-San Yoo ,  Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Tse-Liang Ying

发明人： Chue-San Yoo ,  Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Tse-Liang Ying

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.

摘要翻译： 已经开发了用于在相同的半导体芯片上将用于集成逻辑和DRAM存储器件的厚的绝缘体层中形成的窄直径接触孔的宽高比减小的方法。 减小这些接触孔的纵横比的过程，其特征在于，通过图案化步骤，在逻辑区域中最初形成较小的窄直径的接触孔到有源器件区域，同时还形成自对准的接触开口到源极/漏极 DRAM存储区域中的区域。 在形成钨结构之后，在下部窄直径的接触孔中，多晶硅位线和多晶硅电容器结构通过上层绝缘体层和多晶硅和多晶硅导电层的沉积和图案形成在DRAM存储区域中。 然后在上层绝缘体层中形成上部，小直径的开口，暴露位于下部较窄直径的接触孔中的钨结构的顶表面。 在上部窄直径接触开口中形成上部钨结构完成了通过两级接触孔开口形成的具有减小的纵横比的窄直径开口中的金属结构的形成和两阶段金属填充程序的过程。

公开(公告)号：US6037222A

公开(公告)日：2000-03-14

申请号：US83271

申请日：1998-05-22

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Jenn Ming Huang

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Jenn Ming Huang

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L27/1052 ,  H01L27/10873

摘要： A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology. The method comprises:(a) forming a first gate oxide layer 20, a first polysilicon layer 24, and a first gate cap layer 28 over said logic area 12;(b) forming memory gate structures 34 36 38 40 42A in memory area 14,(c) forming memory LDD regions 50 adjacent to said memory gate structures 24 26 28 40 in said memory area 14;(d) patterning said first gate oxide layer 20, said first polysilicon layer 24 and said first gate cap layer 28 over said logic area forming logic gate structures 20 24A & 20 24B;(e) forming spacers 66;(f) forming logic Source/drain regions 62;(g) using a salicide process to form self-aligned silicide logic S/D contacts 72 to said Source/drain regions 62, and to form self-aligned silicide logic gate contacts 74 to said logic gate structures 20 24B & 20 24A; and(h) forming self aligned polycide contacts 80 to said memory source/drain regions 50.

摘要翻译： 一种制造具有嵌入式逻辑的存储器件的方法。 存储器和逻辑FETs具有两个不同的两个栅极氧化层20 34的厚度。 该方法集成了（1）自杀式接触过程72 74（逻辑器件）和双栅极（N + / P +）逻辑门24A 24B技术与（2）存储器件Polycide与自对准接触80技术。 该方法包括：（a）在所述逻辑区域12上形成第一栅极氧化物层20，第一多晶硅层24和第一栅极覆盖层28; （b）在存储器区域14中形成存储器栅极结构34 36 38 40 42A，（c）在所述存储区域14中形成与所述存储器栅极结构24 26 28 40相邻的存储器LDD区域50; （d）在所述逻辑区域上形成所述第一栅极氧化物层20，所述第一多晶硅层24和所述第一栅极覆盖层28，形成逻辑门结构20A，24A和20BB; （e）形成间隔件66; （f）形成逻辑源极/漏极区域62; （g）使用自对准硅化物工艺将自对准硅化物逻辑S / D触点72形成到所述源极/漏极区62，并且形成到所述逻辑门结构20 24B和20 24A的自对准硅化物逻辑门触点74; 和（h）将自对准的多晶硅触点80形成到所述存储器源极/漏极区50。

公开(公告)号：US5922515A

公开(公告)日：1999-07-13

申请号：US31684

申请日：1998-02-27

申请人： Wen-Chuan Chiang ,  Tse-Liang Ying

发明人： Wen-Chuan Chiang ,  Tse-Liang Ying

IPC分类号： H01L21/768 ,  G03F7/00

CPC分类号： H01L21/76802

摘要： A method of improving the deep contact processing window is described. Semiconductor device structures in and on a semiconductor substrate are covered with a dielectric layer. A polysilicon layer is deposited overlying the dielectric layer. The polysilicon layer is etched away where it is not covered by a photoresist mask to form a polysilicon hard mask. A contact opening is etched through the dielectric layer to the semiconductor substrate where the deep contact is to be made where the dielectric layer is not covered by the polysilicon hard mask. Thereafter the photoresist mask is removed. A photoresist layer is deposited overlying the polysilicon hard mask and filling the contact opening. The polysilicon hard mask and the photoresist layer not within the contact opening are polished away wherein the photoresist layer remaining within the contact opening protects the contact opening from contamination during polishing. Thereafter, the photoresist layer within the contact opening is removed and a metal layer is deposited within the contact opening to complete the deep contact in the fabrication of an integrated circuit device.

摘要翻译： 描述了改善深度接触处理窗口的方法。 半导体衬底中的半导体器件结构被覆盖有电介质层。 沉积覆盖在电介质层上的多晶硅层。 多晶硅层被蚀刻掉，其未被光刻胶掩模覆盖以形成多晶硅硬掩模。 通过电介质层蚀刻接触开口到半导体衬底，在半导体衬底上将进行深度接触，其中电介质层未被多晶硅硬掩模覆盖。 此后，去除光致抗蚀剂掩模。 沉积在多晶硅硬掩模上并填充接触开口的光致抗蚀剂层。 多晶硅硬掩模和不在接触开口内的光致抗蚀剂层被抛光，其中留在接触开口内的光致抗蚀剂层保护接触开口免受抛光期间的污染。 此后，去除接触开口内的光致抗蚀剂层，并且在接触开口内沉积金属层，以在集成电路器件的制造中完成深接触。

公开(公告)号：US5811331A

公开(公告)日：1998-09-22

申请号：US719236

申请日：1996-09-24

申请人： Tse-Liang Ying ,  Mong-Song Liang

发明人： Tse-Liang Ying ,  Mong-Song Liang

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The present invention provides a method of manufacturing a cylindrical capacitor which begins by forming an insulating layer and a passivation layer composed of silicon nitride is over a substrate. A plug contact opening is formed through the passivation layer and the insulating layer. The insulating layer in the plug contact opening is selectively wet etched. The wet etching forms an overhanging portion of the passivation layer. A bottom plug is formed in the contact opening. A first dielectric layer having a cylindrical electrode opening is formed over passivation layer and the plug is exposed. A second polysilicon layer is formed over the first dielectric layer and in the cylindrical openings. A second dielectric layer is formed over the second polysilicon layer and in the cylindrical electrode opening. The second dielectric layer and the second polysilicon layer are planarized. The remaining second polysilicon layer in the cylindrical opening forms a cylindrical capacitor electrode over the bottom electrode plug. The first dielectric layer and the second dielectric layer are etched away. The overhang portion 21 of the passivation layer 20 and the bottom polysilicon plug 32 prevent the etch from etching voids in the underlying insulating layer 14 when the cylindrical electrode 50 is misaligned relative to the plug.

摘要翻译： 本发明提供一种通过形成绝缘层开始的圆柱形电容器的制造方法，并且由氮化硅构成的钝化层在衬底上。 通过钝化层和绝缘层形成插塞接触开口。 插头接触开口中的绝缘层被选择性地湿蚀刻。 湿蚀刻形成钝化层的突出部分。 底塞形成在接触开口中。 在钝化层上形成具有圆柱形电极开口的第一电介质层，并且暴露插头。 第二多晶硅层形成在第一介电层上和圆柱形开口中。 第二电介质层形成在第二多晶硅层上和圆柱形电极开口中。 第二电介质层和第二多晶硅层被平坦化。 圆柱形开口中剩余的第二多晶硅层在底部电极插头上形成圆柱形电容器电极。 第一介电层和第二介电层被蚀刻掉。 当圆柱形电极50相对于插头不对准时，钝化层20的突出部分21和底部多晶硅插塞32防止蚀刻蚀刻下面的绝缘层14中的空隙。

公开(公告)号：USRE43426E1

公开(公告)日：2012-05-29

申请号：US13152124

申请日：2011-06-02

申请人： Tse-Liang Ying ,  Shi-Ming Chen

发明人： Tse-Liang Ying ,  Shi-Ming Chen

IPC分类号： H01L21/00

CPC分类号： H01L33/42 ,  Y10S438/956

摘要： A method for forming a transparent electrode on a visible light-emitting diode is described. A visible light-emitting diode element is provided, and the visible light-emitting diode element has a substrate, an epitaxial structure and a metal electrode. The metal electrode and the epitaxial structure are located on the same side of the substrate, or located respectively on the different sides of the substrate. An ohmic metal layer is formed on a surface of the epitaxial structure. The ohmic metal layer is annealed. The ohmic metal layer is removed to expose the surface of the epitaxial structure. A transparent electrode layer is formed on the exposed surface. A metal pad is formed on the transparent electrode layer.

摘要翻译： 描述了在可见光发光二极管上形成透明电极的方法。 提供了可见光发光二极管元件，可见光发光二极管元件具有基板，外延结构和金属电极。 金属电极和外延结构位于基板的同一侧，或分别位于基板的不同侧。 在外延结构的表面上形成欧姆金属层。 欧姆金属层退火。 去除欧姆金属层以露出外延结构的表面。 在露出的表面上形成透明电极层。 在透明电极层上形成金属焊盘。

公开(公告)号：US07192794B2

公开(公告)日：2007-03-20

申请号：US10938309

申请日：2004-09-09

申请人： Tse-Liang Ying ,  Shi-Ming Chen

发明人： Tse-Liang Ying ,  Shi-Ming Chen

IPC分类号： H01L21/00

CPC分类号： H01L33/42 ,  Y10S438/956

摘要： A method for forming a transparent electrode on a visible light-emitting diode is described. A visible light-emitting diode element is provided, and the visible light-emitting diode element has a substrate, an epitaxial structure and a metal electrode. The metal electrode and the epitaxial structure are located on the same side of the substrate, or located respectively on the different sides of the substrate. An ohmic metal layer is formed on a surface of the epitaxial structure. The ohmic metal layer is annealed. The ohmic metal layer is removed to expose the surface of the epitaxial structure. A transparent electrode layer is formed on the exposed surface. A metal pad is formed on the transparent electrode layer.

摘要翻译： 描述了在可见光发光二极管上形成透明电极的方法。 提供了可见光发光二极管元件，可见光发光二极管元件具有基板，外延结构和金属电极。 金属电极和外延结构位于基板的同一侧，或分别位于基板的不同侧。 在外延结构的表面上形成欧姆金属层。 欧姆金属层退火。 去除欧姆金属层以露出外延结构的表面。 在露出的表面上形成透明电极层。 在透明电极层上形成金属焊盘。

公开(公告)号：US06207492B1

公开(公告)日：2001-03-27

申请号：US09587466

申请日：2000-06-05

申请人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Kevin Chiang

发明人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Kevin Chiang

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10873

摘要： A process for forming logic devices with salicide shapes on gate structures, as well as on heavily doped source/drain regions, while simultaneously forming embedded DRAM devices with salicide shapes only on gate structures, has been developed. The process features silicon oxide blocking shapes, formed in the spaces between gate structures, in the embedded DRAM device region. The silicon oxide blocking shapes are formed using a high density plasma deposition procedure which deposits a thick silicon oxide layer in the narrow spaces between gate structures in the embedded DRAM device region, and a thin silicon oxide layer in the wider spaces between gate structures in the logic device region, and on the top surface of all gate structures. A blanket, dry etch procedure is then employed to remove the thin silicon oxide layers from the top surface of all gate structures, as well as from the spaces between gate structures in the logic device region, while forming the desired silicon oxide blocking shapes between gate structures in the embedded DRAM device region, therefore allowing subsequent salicide shapes to be formed only on the top surface of gate structures, and on heavily doped source/drain regions in the logic device region.

摘要翻译： 已经开发了用于在栅极结构上以及重掺杂的源极/漏极区域上形成具有硅化物形状的逻辑器件的过程，同时仅在栅极结构上形成具有硅化物形状的嵌入式DRAM器件。 该工艺在嵌入式DRAM器件区域中具有形成在栅极结构之间的空间中的氧化硅阻挡形状。 使用高密度等离子体沉积方法形成氧化硅阻挡形状，该方法在嵌入式DRAM器件区域中的栅极结构之间的狭窄空间中沉积厚的氧化硅层，并且在栅极结构中的较宽空间中沉积薄的氧化硅层 逻辑器件区域，并在所有栅极结构的顶表面上。 然后采用全面的干蚀刻方法从所有栅极结构的顶表面以及逻辑器件区域中的栅极结构之间的空间中移除薄氧化硅层，同时在栅极之间形成期望的氧化硅阻挡形状 结构，因此允许仅在栅极结构的顶表面上以及在逻辑器件区域中的重掺杂的源/漏区上形成随后的自对准硅化物形状。

公开(公告)号：US06194234B1

公开(公告)日：2001-02-27

申请号：US09324925

申请日：1999-06-04

申请人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

发明人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

IPC分类号： G01R3126

CPC分类号： H01L22/12

摘要： A new method based on measuring the weight of a wafer (on which the layer of HSG has been deposited) before (W1) and after (W2) the surface of the HSG layer is coated with a layer of either photoresist or SOG. The difference delta W=W2−W1 provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG. This new method can also be based on measuring the weight W of rejected or dropped PR or SOG after the surface of the HSG layer has been coated with a layer of either photoresist or SOG. The weight of the rejected or dropped PR or SOG also provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG.

摘要翻译： 基于测量在HSG层的表面之前（W1）和之后（W2）的晶片（其上沉积了HSG的层）的重量的新方法涂覆有光致抗蚀剂或SOG层。 差值ΔW= W2-W1提供HSG沉积层的表面的粗糙度或平滑度的指标。 这种新方法也可以基于测量在HSG层的表面已经涂覆有光致抗蚀剂或SOG层之后的被拒绝或掉落的PR或SOG的重量W。 拒收或掉落的PR或SOG的重量也提供HSG沉积层的表面的粗糙度或平滑度的指标。