公开(公告)号：US06187659B1

公开(公告)日：2001-02-13

申请号：US09368861

申请日：1999-08-06

申请人： Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

发明人： Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC分类号： H01L214763

CPC分类号： H01L27/10855 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897

摘要： A new method is provided to create a gradated dopant concentration in the contact plug of DRAM devices whereby a high dopant concentration is present at the bottom of the plug and a low dopant concentration is present at the top of the plug. Two layers of dielectric are deposited; the upper layer serves as a layer to adjust the dopant concentration in the lower layer. This adjustment is done by Rapid Thermal anneal of both layers of dielectric. After the dopant concentration has been adjusted, the upper layer of dielectric is removed and the upper section of the contact node is formed using lightly doped poly. The high dopant concentration at the bottom of the contact plug results in low contact resistance between the plug and the underlying silicon substrate. A low dopant concentration at the top surface of the contact plug results in low oxidation of the surface of the plug.

摘要翻译： 提供了一种新的方法来在DRAM器件的接触插塞中产生渐变的掺杂剂浓度，由此在插塞的底部存在高的掺杂剂浓度，并且在插头的顶部存在低的掺杂剂浓度。 沉积两层电介质; 上层用作调整下层中的掺杂剂浓度的层。 这种调整是通过两层电介质的快速热退火进行的。 在调整掺杂剂浓度之后，去除电介质的上层，并且使用轻掺杂的多晶形成接触节点的上部。 接触插塞底部的高掺杂剂浓度导致插头和底层硅衬底之间的低接触电阻。 在接触塞顶表面的低掺杂剂浓度导致插塞表面的低氧化。

公开(公告)号：US06168984A

公开(公告)日：2001-01-02

申请号：US09419103

申请日：1999-10-15

申请人： Chue-San Yoo ,  Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Tse-Liang Ying

发明人： Chue-San Yoo ,  Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Tse-Liang Ying

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.

摘要翻译： 已经开发了用于在相同的半导体芯片上将用于集成逻辑和DRAM存储器件的厚的绝缘体层中形成的窄直径接触孔的宽高比减小的方法。 减小这些接触孔的纵横比的过程，其特征在于，通过图案化步骤，在逻辑区域中最初形成较小的窄直径的接触孔到有源器件区域，同时还形成自对准的接触开口到源极/漏极 DRAM存储区域中的区域。 在形成钨结构之后，在下部窄直径的接触孔中，多晶硅位线和多晶硅电容器结构通过上层绝缘体层和多晶硅和多晶硅导电层的沉积和图案形成在DRAM存储区域中。 然后在上层绝缘体层中形成上部，小直径的开口，暴露位于下部较窄直径的接触孔中的钨结构的顶表面。 在上部窄直径接触开口中形成上部钨结构完成了通过两级接触孔开口形成的具有减小的纵横比的窄直径开口中的金属结构的形成和两阶段金属填充程序的过程。

公开(公告)号：US5922515A

公开(公告)日：1999-07-13

申请号：US31684

申请日：1998-02-27

申请人： Wen-Chuan Chiang ,  Tse-Liang Ying

发明人： Wen-Chuan Chiang ,  Tse-Liang Ying

IPC分类号： H01L21/768 ,  G03F7/00

CPC分类号： H01L21/76802

摘要： A method of improving the deep contact processing window is described. Semiconductor device structures in and on a semiconductor substrate are covered with a dielectric layer. A polysilicon layer is deposited overlying the dielectric layer. The polysilicon layer is etched away where it is not covered by a photoresist mask to form a polysilicon hard mask. A contact opening is etched through the dielectric layer to the semiconductor substrate where the deep contact is to be made where the dielectric layer is not covered by the polysilicon hard mask. Thereafter the photoresist mask is removed. A photoresist layer is deposited overlying the polysilicon hard mask and filling the contact opening. The polysilicon hard mask and the photoresist layer not within the contact opening are polished away wherein the photoresist layer remaining within the contact opening protects the contact opening from contamination during polishing. Thereafter, the photoresist layer within the contact opening is removed and a metal layer is deposited within the contact opening to complete the deep contact in the fabrication of an integrated circuit device.

摘要翻译： 描述了改善深度接触处理窗口的方法。 半导体衬底中的半导体器件结构被覆盖有电介质层。 沉积覆盖在电介质层上的多晶硅层。 多晶硅层被蚀刻掉，其未被光刻胶掩模覆盖以形成多晶硅硬掩模。 通过电介质层蚀刻接触开口到半导体衬底，在半导体衬底上将进行深度接触，其中电介质层未被多晶硅硬掩模覆盖。 此后，去除光致抗蚀剂掩模。 沉积在多晶硅硬掩模上并填充接触开口的光致抗蚀剂层。 多晶硅硬掩模和不在接触开口内的光致抗蚀剂层被抛光，其中留在接触开口内的光致抗蚀剂层保护接触开口免受抛光期间的污染。 此后，去除接触开口内的光致抗蚀剂层，并且在接触开口内沉积金属层，以在集成电路器件的制造中完成深接触。

公开(公告)号：US06306767B1

公开(公告)日：2001-10-23

申请号：US09584111

申请日：2000-05-31

申请人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Ming-Hsiang Chiang

发明人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Ming-Hsiang Chiang

IPC分类号： H01L21302

CPC分类号： H01L27/10888 ,  H01L21/32139 ,  H01L27/10811

摘要： Within a method for forming a patterned layer there is first provided a topographic substrate. There is then formed conformally over the topographic substrate a blanket target layer formed of a target material, where the blanket target layer has a lower substantially horizontal portion, an upper substantially horizontal portion and an intermediate portion therebetween. There is then formed upon the lower substantially horizontal portion of the blanket target layer a first masking layer formed of a first masking material and formed upon the upper substantially horizontal portion of the blanket target layer a second masking layer formed of a second masking material. There is then etched, while employing an etch method having an enhanced sequential selectivity for the first masking material and the target material with respect to the second masking material, the first masking layer and the lower substantially horizontal portion of the blanket target layer to form a patterned target layer which leaves exposed a portion of the substrate beneath the lower horizontal portion of the blanket target layer while leaving unetched the upper substantially horizontal portion of the blanket target layer. The method is particularly useful for forming patterned capacitor plate layers.

摘要翻译： 在形成图案层的方法中，首先提供地形衬底。 然后，在地形基底上形成由目标材料形成的覆盖目标层，其中覆盖层目标层具有下部基本水平的部分，上部基本水平的部分和在其间的中间部分。 然后，在覆盖目标层的下部基本水平的部分上形成由第一掩模材料形成并形成在覆盖目标层的上部基本水平的部分上的第一掩蔽层，第二掩蔽层由第二掩蔽材料形成。 然后蚀刻，同时采用对于第一掩蔽材料和靶材料相对于第二掩蔽材料具有增强的顺序选择性的蚀刻方法，覆盖目标层的第一掩蔽层和下部基本水平的部分，以形成 图案化目标层，其在衬底目标层的下部水平部分的下方露出衬底的一部分，同时保留未覆盖的覆盖目标层的上部基本水平的部分。 该方法对于形成图案化电容器板层特别有用。

公开(公告)号：US06174802B1

公开(公告)日：2001-01-16

申请号：US09342042

申请日：1999-06-28

申请人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

发明人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

IPC分类号： H01L214763

CPC分类号： H01L21/76897

摘要： A method for forming a self aligned contact without key holes using a two step contact deposition. The process begins by providing a semiconductor structure having conductive structures (such as bit lines) thereover with sidewalls and having a contact area adjacent to the conductive structures. The conductive structures comprise at least one conductive layer with a hard mask thereover. A spacer layer is formed over the hard mask and the substrate structure and anisotropically etched to form sidewall spacers on the sidewalls of the conductive structure. A second dielectric (IPO) layer is formed over the sidewall spacers, the hard mask, and the substrate structure, whereby the second dielectric layer has a keyhole. A contact opening is formed in the second dielectric layer over the contact area. A first contact layer having poor step coverage is formed in the contact openings and over the second dielectric layer, thereby plugging the keyhole without filling it. A second contact layer is formed over the first contact layer.

摘要翻译： 使用两步接触沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有导电结构（例如位线）的半导体结构，其具有侧壁并且具有与导电结构相邻的接触区域。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和衬底结构之上形成间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成侧壁间隔物。 在侧壁间隔物，硬掩模和基板结构上方形成第二电介质层（IPO），由此第二介电层具有锁孔。 在接触区域上的第二电介质层中形成接触开口。 在接触开口和第二电介质层上形成具有差的台阶覆盖率的第一接触层，从而在不填充锁孔的情况下封闭钥匙孔。 在第一接触层上形成第二接触层。

公开(公告)号：US06287939B1

公开(公告)日：2001-09-11

申请号：US09216789

申请日：1998-12-21

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76895

摘要： The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI “kink effect,” as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N2 ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate. The nitride layer is removed. Then, the pad oxide layer and portions of the fill oxide regions are removed using the buried oxynitride layer as an etch stop, forming shallow trench isolations.

摘要翻译： 本发明提供一种用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法。 本发明还提供了对STI“扭结效应”的免疫力以及与氮化相关的益处。 该过程开始于在半导体衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成氮化物层。 图案化氮化物层，衬垫氧化物层和半导体衬底以形成沟槽。 接下来，在氮化物层，衬垫氧化物层和半导体衬底之上形成填充氧化物层。 填充氧化物层进行化学机械抛光，在氮化物层上停止形成填充氧化物区域。 将N 2离子注入填充氧化物区域。 进行退火以形成掩埋的氮氧化物层。 掩埋的氧氮化物层部分地高于半导体衬底的顶表面的高度，并且部分地低于半导体衬底的顶表面的水平。 去除氮化物层。 然后，使用掩埋氧氮化物层作为蚀刻停止层，去除衬垫氧化物层和填充氧化物区域的部分，形成浅沟槽隔离。

公开(公告)号：US06214715B1

公开(公告)日：2001-04-10

申请号：US09349841

申请日：1999-07-08

申请人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

发明人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC分类号： H01L2144

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91 ,  H01L28/92

摘要： This invention provides a method for forming a self aligned contact without key holes using a two step sidewall spacer deposition. The process begins by providing a semiconductor structure having a device layer, a first inter poly oxide layer (IPO-1), and a conductive structure (such as a bit line) thereover, and having a contact area on the device layer adjacent to the conductive structure. The semiconductor structure can further include an optional etch stop layer overlying the first inter poly oxide layer. The conductive structure comprises at least one conductive layer with a hard mask thereover. A first spacer layer is formed over the hard mask and the IPO-1 layer and anisotropically etched to form first sidewall spacers on the sidewalls of the conductive structure up to a level above the bottom of the hard mask and below the level of the top of the hard mask such that the profile of the first sidewall spacers are not concave at any point. A second spacer layer is formed over the first sidewall spacers and anisotropically etched to form second sidewall spacers, having a profile that is not concave at any point. A second inter poly oxide layer is formed over the second sidewall spacers, the hard mask, and the IPO-1 layer, whereby the second inter poly oxide layer is free from key holes. A contact opening is formed in the second inter poly oxide layer and the first inter poly oxide layer over the contact area. A contact plug is formed in the contact openings.

摘要翻译： 本发明提供一种用于使用两步侧壁间隔物沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有器件层，第一多晶硅氧化物层（IPO-1）和导电结构（例如位线）的半导体结构，并且在与其相邻的器件层上具有接触区域 导电结构。 半导体结构还可以包括覆盖在第一多晶硅氧化物层上的任选的蚀刻停止层。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和IPO-1层上形成第一间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成直到硬掩模的底部以上的水平并且低于 硬掩模，使得第一侧壁隔片的轮廓在任何点都不是凹的。 第二间隔层形成在第一侧壁间隔物上并且各向异性蚀刻以形成第二侧壁间隔物，其具有在任何点处不凹的轮廓。 在第二侧壁间隔物，硬掩模和IPO-1层上形成第二多晶硅氧化物层，由此第二多晶氧化物层没有键孔。 在接触区域上的第二多晶氧化物层和第一多晶氧化物层中形成接触开口。 在接触开口中形成接触塞。

公开(公告)号：US6080637A

公开(公告)日：2000-06-27

申请号：US206736

申请日：1998-12-07

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Yeh Shih

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Yeh Shih

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate. An insulator deposition, filling openings, and recesses, in the composite insulator layer, and filling the shallow trench, followed by removal of excess insulator fill, on the top surface of the composite insulator layer, results in the formation of a "T" shape insulator, comprised of an insulator shape, in the shallow trench, and comprised of a wider insulator shape, located in the composite insulator shape, with the lateral recess in the thick silicon nitride layer, and with the wider insulator shape, overlying the narrow, insulator shape, in the shallow trench. The insulator, in the shallow trench, is protected from the procedure used to remove components of the composite insulator layer, by the wider insulator shape.

摘要翻译： 已经开发了在半导体衬底中形成绝缘体填充的浅沟槽的方法，其中浅沟槽中的绝缘体层不暴露于用于移除限定复合绝缘体层的程序。 该工艺的特征是在半导体衬底中产生在厚氮化硅层中用作复合绝缘体层的组分的横向凹槽，其中复合绝缘体层用于随后定义浅沟槽。 在复合绝缘体层中的绝缘体沉积，填充开口和凹陷，以及填充浅沟槽，然后在复合绝缘体层的顶表面上除去多余的绝缘体填充物，导致形成“T”形 绝缘体，由绝缘体形状构成，位于浅沟槽中，并且由更宽的绝缘体形状组成，位于复合绝缘体形状中，侧壁凹陷在厚氮化硅层中，并且具有更宽的绝缘体形状， 绝缘体形状，在浅沟槽。 通过更宽的绝缘体形状，在浅沟槽中的绝缘体被保护以避免用于去除复合绝缘体层的部件的程序。

公开(公告)号：US06194234B1

公开(公告)日：2001-02-27

申请号：US09324925

申请日：1999-06-04

申请人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

发明人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Yu-Hua Lee

IPC分类号： G01R3126

CPC分类号： H01L22/12

摘要： A new method based on measuring the weight of a wafer (on which the layer of HSG has been deposited) before (W1) and after (W2) the surface of the HSG layer is coated with a layer of either photoresist or SOG. The difference delta W=W2−W1 provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG. This new method can also be based on measuring the weight W of rejected or dropped PR or SOG after the surface of the HSG layer has been coated with a layer of either photoresist or SOG. The weight of the rejected or dropped PR or SOG also provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG.

摘要翻译： 基于测量在HSG层的表面之前（W1）和之后（W2）的晶片（其上沉积了HSG的层）的重量的新方法涂覆有光致抗蚀剂或SOG层。 差值ΔW= W2-W1提供HSG沉积层的表面的粗糙度或平滑度的指标。 这种新方法也可以基于测量在HSG层的表面已经涂覆有光致抗蚀剂或SOG层之后的被拒绝或掉落的PR或SOG的重量W。 拒收或掉落的PR或SOG的重量也提供HSG沉积层的表面的粗糙度或平滑度的指标。

公开(公告)号：US08617949B2

公开(公告)日：2013-12-31

申请号：US13267424

申请日：2011-10-06

申请人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.

摘要翻译： 片上系统装置包括第一区域中的第一电容器，第二区域中的第二电容器，并且还可以包括第三区域中的第三电容器，以及附加区域中的任何附加数量的电容器。 电容器可以具有不同的形状和尺寸。 区域可以包括多于一个的电容器。 区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。 所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。 电容器绝缘体可以具有不同数量的亚层，形成不同的材料或厚度。 电容器可以形成在层间电介质层中或在金属间介电层中。 这些区域可以是混合信号区域，模拟区域等。