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16 条记录 (耗时 0.024 秒)

    Semiconductor device and method of producing same
    11.
    发明授权
    Semiconductor device and method of producing same 失效
    半导体装置及其制造方法

    公开(公告)号：US6025652A

    公开(公告)日：2000-02-15

    申请号：US81680

    申请日：1998-05-20

    申请人： Kazuhiro Tsukamoto

    发明人： Kazuhiro Tsukamoto

    IPC分类号： H01L21/027 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/544 ,  H01L23/48

    CPC分类号： H01L27/10844 ,  H01L27/10852

    摘要： In a semiconductor device having a mark opening portion such as an alignment mark and an overlay mark, a BPSG film formed by patterning on this mark opening portion interposing a first conductive film is covered by a second conductive film; and the BPSG film serves as a core of a cylindrical storage node and is removed after the second conductive film is formed in a shape of sidewall by a vapor phase HF treatment process, whereby a conductive contaminant is not peeled off at the time of removing the BPSG film, wherein a drop of yield can be restricted.

    摘要翻译： 在具有诸如对准标记和重叠标记的标记开口部分的半导体器件中，通过在插入第一导电膜的该标记开口部分上图案化形成的BPSG膜被第二导电膜覆盖; 并且BPSG膜用作圆柱形存储节点的核心，并且在通过气相HF处理工艺在第二导电膜形成为侧壁形状之后被去除，由此在去除导电性污染物时不会剥离导电性污染物 BPSG膜，其中可以限制一滴产率。

    Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer
    12.
    发明授权
    Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer 失效
    形成具有在存储单元与层间绝缘层之间的接触区域的半导体存储器件的方法

    公开(公告)号：US5580813A

    公开(公告)日：1996-12-03

    申请号：US483037

    申请日：1995-06-07

    申请人： Atsushi Hachisuka ,  Kazuhiro Tsukamoto ,  Mitsuya Kinoshita

    发明人： Atsushi Hachisuka ,  Kazuhiro Tsukamoto ,  Mitsuya Kinoshita

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10817

    摘要： A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The lower layer interconnection film 109 has a concave shape. A through hole 95a is formed in a silicon oxide film 93 reaching the bottom of the concave shape lower layer interconnection film 109. The depth of the through hole 95a is greater in comparison with the case where a through hole is formed on an upper face portion 123a of the silicon oxide film 123. Because the depth of through hole 95a is great, the thickness of the tungsten film 101a formed in through hole 95a becomes thicker. This eliminates the problem that all the tungsten film 101a in the through hole 95a, and then a portion of the lower layer interconnection film 109 are overetched. Therefore, electrical connection between the upper layer interconnection layer 103a and the lower layer interconnection layer 109 can be ensured.

    摘要翻译： 在场氧化膜107a和氧化硅膜123上延伸的单元板91的一部分被称为下层互连膜109.下层布线膜109具有凹形。 在到达凹形下层互连膜109的底部的氧化硅膜93中形成通孔95a。与在上表面部分形成通孔的情况相比，通孔95a的深度更大 123a。由于通孔95a的深度大，所以形成在通孔95a中的钨膜101a的厚度变厚。 这消除了通孔95a中的所有钨膜101a以及下层互连膜109的一部分被过蚀刻的问题。 因此，可以确保上层布线层103a和下层布线层109之间的电连接。

    Semiconductor device having redundant circuit
    13.
    发明授权
    Semiconductor device having redundant circuit 失效
    具有冗余电路的半导体器件

    公开(公告)号：US5578861A

    公开(公告)日：1996-11-26

    申请号：US357298

    申请日：1994-12-13

    申请人： Mitsuya Kinoshita ,  Atsushi Hachisuka ,  Kazuhiro Tsukamoto

    发明人： Mitsuya Kinoshita ,  Atsushi Hachisuka ,  Kazuhiro Tsukamoto

    IPC分类号： H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L27/10 ,  H01L23/62 ,  H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002

    摘要： In a semiconductor device, a connection conductive layer is formed by patterning on a p-type semiconductor substrate. A silicon nitride film is formed on the connection conductive layer with an insulating layer. A silicon oxide film is formed on the silicon nitride film. The silicon oxide film is provided with a hole. The silicon nitride film is exposed at a bottom of the hole. The hole is located immediately above the connection conductive layer. Thereby, a thickness of the insulating layer on a fuse element which can be blown can be controlled easily in the semiconductor device.

    摘要翻译： 在半导体器件中，通过在p型半导体衬底上图案化形成连接导电层。 在具有绝缘层的连接导电层上形成氮化硅膜。 在氮化硅膜上形成氧化硅膜。 氧化硅膜设置有孔。 氮化硅膜暴露在孔的底部。 孔位于连接导电层的正上方。 由此，可以在半导体器件中容易地控制能够熔断的熔丝元件上的绝缘层的厚度。

    Abutment device for a key switch arrangement operable with both hammer-equipped and hammerless keyboards for electronic musical instruments
    14.
    发明授权
    Abutment device for a key switch arrangement operable with both hammer-equipped and hammerless keyboards for electronic musical instruments 失效
    用于键盘开关装置的基台装置，可与用于电子乐器的锤装备和无锤键盘一起操作

    公开(公告)号：US5571983A

    公开(公告)日：1996-11-05

    申请号：US152706

    申请日：1993-11-16

    申请人： Tsutomu Yamaguchi ,  Kazuhiro Tsukamoto

    发明人： Tsutomu Yamaguchi ,  Kazuhiro Tsukamoto

    IPC分类号： G10B3/12 ,  G10C3/12 ,  G10F1/02 ,  G10H1/34 ,  G10H3/00

    CPC分类号： G10H1/346 ,  Y10S84/07

    摘要： A keyboard device for an electronic musical instrument comprises a keyboard chassis, keys rotatively arranged on the keyboard chassis, and a key switch arranged beneath each of the keys for detecting a key status of each key. Each key has a switch-depressing projection arranged just above the key switch, and a hammer-depressing projection for depressing a hammer when the hammer is provided, with the switch-depressing projection and the hammer-depressing projection being formed adjacent to each other in one piece.

    摘要翻译： 一种用于电子乐器的键盘装置包括键盘机箱，旋转地布置在键盘机箱上的按键和设置在每个键下方的键开关，用于检测每个键的键状态。 每个键具有刚好在钥匙开关上方布置的开关按压突起，以及用于在设置锤时按下锤子的捶击式突起，其中开关按压突起和槌击压突起彼此相邻地形成 一块。

    Semiconductor memory device with contact region intermediate memory cell and peripheral circuit
    15.
    发明授权
    Semiconductor memory device with contact region intermediate memory cell and peripheral circuit 失效
    具有接触区中间存储单元和外围电路的半导体存储器件

    公开(公告)号：US5448512A

    公开(公告)日：1995-09-05

    申请号：US44676

    申请日：1993-04-09

    申请人： Atsushi Hachisuka ,  Kazuhiro Tsukamoto ,  Mitsuya Kinoshita

    发明人： Atsushi Hachisuka ,  Kazuhiro Tsukamoto ,  Mitsuya Kinoshita

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  G11C11/401

    CPC分类号： H01L27/10817

    摘要： A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The lower layer interconnection film 109 has a concave shape. A through hole 95a is formed in a silicon oxide film 93 reaching the bottom of the concave shape lower layer interconnection film 109. The depth of the through hole 95a is greater in comparison with the case where a through hole is formed on an upper face portion 123a of the silicon oxide film 123. Because the depth of through hole 95a is great, the thickness of the tungsten film 101a formed in through hole 95a becomes thicker. This eliminates the problem that all the tungsten film 101a in the through hole 95a, and then a portion of the lower layer interconnection film 109 are overetched. Therefore, electrical connection between the upper layer interconnection layer 103a and the lower layer interconnection layer 109 can be ensured.

    摘要翻译： 在场氧化膜107a和氧化硅膜123上延伸的单元板91的一部分被称为下层互连膜109.下层布线膜109具有凹形。 在到达凹形下层互连膜109的底部的氧化硅膜93中形成通孔95a。与在上表面部分形成通孔的情况相比，通孔95a的深度更大 123a。由于通孔95a的深度大，所以形成在通孔95a中的钨膜101a的厚度变厚。 这消除了通孔95a中的所有钨膜101a以及下层互连膜109的一部分被过蚀刻的问题。 因此，可以确保上层布线层103a和下层布线层109之间的电连接。