Generation of a stable reference clock frequency from a base clock
frequency that may vary depending on source
    11.
    发明授权
    Generation of a stable reference clock frequency from a base clock frequency that may vary depending on source 失效
    从基本时钟频率产生稳定的参考时钟频率,这可能因源而异

    公开(公告)号:US6070248A

    公开(公告)日:2000-05-30

    申请号:US989986

    申请日:1997-12-12

    CPC classification number: G06F1/08

    Abstract: A clock signal generator within an electronic device locally generates a reference clock signal having a reference frequency from a base clock signal having a base frequency. The base clock signal is from a base signal source that is external to the electronic device, and the base frequency of the base clock signal may vary depending on the base signal source. The present invention includes a plurality of frequency dividers which are coupled to the base signal source. Each of the frequency dividers outputs a divided clock signal having a respective frequency that is the base frequency divided by a respective factor. A multiplexer accepts the value of the base frequency of the base clock signal as stored within a storage device that is external to the electronic device. The multiplexer then selects as the reference clock signal a divided clock signal having a respective frequency that is closest to the reference frequency depending on the value of the base frequency. In this manner, a reference clock signal having a stable reference frequency is generated for the electronic device despite possible variations in the base frequency of the base clock signal. The present invention may be used to particular advantage when the electronic device is an Ethernet computer network peripheral device coupled between a computer host system and a computer network, and when the base signal source is from the computer host system.

    Abstract translation: 电子设备内的时钟信号发生器本地从具有基本频率的基本时钟信号中产生具有参考频率的参考时钟信号。 基本时钟信号来自电子设备外部的基本信号源,并且基本时钟信号的基本频率可以根据基本信号源而变化。 本发明包括耦合到基本信号源的多个分频器。 每个分频器输出具有相应频率的分频时钟信号,该频率是基本频率除以相应因子。 多路复用器接收存储在电子设备外部的存储设备内的基本时钟信号的基本频率的值。 然后,多路复用器根据基本频率的值选择具有最接近参考频率的相应频率的分频时钟信号作为参考时钟信号。 以这种方式,尽管基本时钟信号的基本频率有可能的变化,但是为电子设备产生具有稳定参考频率的参考时钟信号。 当电子设备是耦合在计算机主机系统和计算机网络之间以及当基本信号源来自计算机主机系统的以太网计算机网络外围设备时,本发明可以被用于特别的优点。

    Method and apparatus for allowing a remote node to awaken a sleeping
node of a network
    12.
    发明授权
    Method and apparatus for allowing a remote node to awaken a sleeping node of a network 失效
    允许远程节点唤醒网络的休眠节点的方法和装置

    公开(公告)号:US6049885A

    公开(公告)日:2000-04-11

    申请号:US881067

    申请日:1997-06-24

    CPC classification number: G06F1/3209 H04L12/12 Y02B60/32 Y02B60/34

    Abstract: A system and method for remotely waking up a device connected to a local area network (LAN) is disclosed. A special data packet is disclosed wherein the destination address of the packet is embedded at least 16 consecutive times within the data field of the packet. When this particular type of packet is transmitted on the LAN, it is first decoded by the I/O subsystem of the device to determine whether or not it is a remote wake-up packet. After determining that the packet received is a remote wake-up packet, a wake-up enable line is activated thereby taking the system out of its low power mode, for providing further processing of future received packets.

    Abstract translation: 公开了用于远程唤醒连接到局域网(LAN)的设备的系统和方法。 公开了一种特殊数据分组,其中分组的目的地地址至少在数据包的数据字段内嵌入16次。 当这种特定类型的分组在LAN上发送时,首先由设备的I / O子系统解码,以确定它是否是远程唤醒分组。 在确定接收到的分组是远程唤醒分组之后,激活唤醒使能线,从而使系统脱离其低功率模式,以提供未来接收分组的进一步处理。

    PACKET VALIDATION IN VIRTUAL NETWORK INTERFACE ARCHITECTURE
    13.
    发明申请
    PACKET VALIDATION IN VIRTUAL NETWORK INTERFACE ARCHITECTURE 有权
    虚拟网络接口架构中的分组验证

    公开(公告)号:US20100049876A1

    公开(公告)日:2010-02-25

    申请号:US12612078

    申请日:2009-11-04

    Abstract: Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.

    Abstract translation: 大体上描述了一种从计算设备接收数据包以便传输到网络上的网络接口设备,具有一定特性的数据分组仅在发送队列具有发送具有该特性的分组的权限时发送分组。 数据包特征可以包括传输协议号,源和目的端口号,源和目的IP地址。 基于建立队列的进程的权限级别,可以通过内核例程在建立传输队列时将授权编程到NIC中。 以这种方式,用户进程可以使用不受信任的用户级协议栈来发起到网络上的数据传输,而NIC保护系统或网络的其余部分免受某些种类的折中。

    Transmit rate pacing system and method
    14.
    发明申请
    Transmit rate pacing system and method 有权
    发送速率起搏系统及方法

    公开(公告)号:US20070174511A1

    公开(公告)日:2007-07-26

    申请号:US11329444

    申请日:2006-01-11

    CPC classification number: G06F13/28

    Abstract: System and method of a pace engine for governing the different transmission rates tailored for different connections by rate pacing a plurality of queues are described. Roughly described, the pace engine includes a binning controller for receiving queues from a transmit DMA queue manager and determines the earliest allowed time for a particular queue that is stored and paced in a Work Bin, a Fast Bin, or a Slow Bin. A pace table stores information about the minimum inter-packet-gap for each connection that is coupled to the transmit DMA queue manager. A timer is coupled to the binning controller with a multi-bit continuous counter that increments at a predetermined time unit and wraps around after a predetermined amount of time.

    Abstract translation: 描述了用于通过速率起搏多个队列来为不同连接量身定制的不同传输速率的步调引擎的系统和方法。 粗略地描述,速度引擎包括用于从发送DMA队列管理器接收队列的分档控制器,并且确定在工作仓,快速仓或慢速仓中存储和起搏的特定队列的最早允许时间。 步速表存储关于耦合到发送DMA队列管理器的每个连接的最小间隔间隔的信息。 定时器与具有多位连续计数器的分箱控制器耦合,该计数器以预定时间单位递增并在预定时间量之后卷绕。

    Packet validation in virtual network interface architecture

    公开(公告)号:US20060248234A1

    公开(公告)日:2006-11-02

    申请号:US11116018

    申请日:2005-04-27

    Abstract: Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.

    Multi-phase EEPROM reading for network interface initialization
    18.
    发明授权
    Multi-phase EEPROM reading for network interface initialization 有权
    用于网络接口初始化的多相EEPROM读数

    公开(公告)号:US06651172B1

    公开(公告)日:2003-11-18

    申请号:US09321842

    申请日:1999-05-28

    CPC classification number: G06F9/4411

    Abstract: A novel method is provided for initializing a data processing system having registers programmable with configuration data read from a non-volatile memory at power-up. The method includes segmenting the non-volatile memory into a first portion for storing first data, and a second portion for storing second data having lower priority than the first data. The first portion is smaller than the second portion. The first data are read from the first portion to program a first group of registers. Thereafter, the second data are read from the second portion to program a second group of registers. As a result, a host is enabled to access the first group of registers, while the second data are being read from the second memory portion.

    Abstract translation: 提供一种新颖的方法来初始化具有可编程的寄存器的数据处理系统,该寄存器在上电时从非易失性存储器读取的配置数据可编程。 该方法包括将非易失性存储器分割成用于存储第一数据的第一部分,以及用于存储具有比第一数据优先级低的第二数据的第二部分。 第一部分小于第二部分。 从第一部分读取第一数据以对第一组寄存器进行编程。 此后,从第二部分读取第二数据以编程第二组寄存器。 结果,主机能够访问第一组寄存器,而第二数据正在从第二存储器部分读取。

    Architecture and method for flushing non-transmitted portions of a data frame from a transmitted FIFO buffer
    19.
    发明授权
    Architecture and method for flushing non-transmitted portions of a data frame from a transmitted FIFO buffer 有权
    用于从发送的FIFO缓冲器冲洗数据帧的未发送部分的架构和方法

    公开(公告)号:US06542512B1

    公开(公告)日:2003-04-01

    申请号:US09346745

    申请日:1999-07-02

    Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data. The transmit memory management unit, in response to the flush transmit buffer signal, sets an incremented transmit buffer pointer value to a buffer pointer value corresponding to a next transmit data stored in the transmit buffer.

    Abstract translation: 分组交换网络中的网络交换机包括多个网络交换机端口,每个网络交换机端口被配置为在介质接口和网络交换机之间发送和接收数据分组。 网络交换机端口包括符合IEEE 802.3标准的传输状态机和接收状态机,其配置用于分别向介质接口(例如简化介质独立接口)发送和接收网络数据。 网络交换机端口还包括配置用于分别在发送和接收状态机与随机接入发送缓冲器和随机接入接收缓冲器之间选择性地传送网络数据的存储器管理单元。 发送状态机响应于发送发送数据中检测到的错误,向发送存储器管理单元输出清空发送缓冲器信号。 发送存储器管理单元响应于刷新发送缓冲器信号,将增加的发送缓冲器指针值设置为对应于存储在发送缓冲器中的下一个发送数据的缓冲器指针值。

    Method and apparatus for reclaiming buffers using a single buffer bit
    20.
    发明授权
    Method and apparatus for reclaiming buffers using a single buffer bit 有权
    使用单个缓冲位来回收缓冲区的方法和装置

    公开(公告)号:US06504846B1

    公开(公告)日:2003-01-07

    申请号:US09315724

    申请日:1999-05-21

    CPC classification number: H04L47/15 H04L49/30 H04L49/3027 H04L49/351 H04L49/90

    Abstract: A method and apparatus are disclosed for reclaiming frame buffers used to store data frames received by a network switch. The apparatus includes a multicopy queue for queuing entries corresponding to received data frames which must be transmitted by multiple output ports of the network switch, a free buffer queue for queuing frame pointers that identify locations in an external memory where reclaimed frame buffers are located, and a multicopy circuit that retrieves entries from the multicopy queue and determines if all copies of a received data frame have been transmitted by the specified output ports. The multicopy circuit also reclaims one or more frame buffers, based on the size of the received data frame. The present invention allows efficient reclaiming of frame buffers regardless of whether the received data frame is stored in a single frame buffer or multiple frame buffers.

    Abstract translation: 公开了用于回收用于存储由网络交换机接收的数据帧的帧缓冲器的方法和装置。 该装置包括用于排队对应于必须由网络交换机的多个输出端口发送的数据帧的条目的多拷贝队列,用于排队识别在回收的帧缓冲器所在的外部存储器中的位置的空闲缓冲器队列,以及 多拷贝电路,从多拷贝队列检索条目,并确定接收的数据帧的所有副本是否已由指定的输出端口发送。 多拷贝电路还基于接收的数据帧的大小回收一个或多个帧缓冲器。 本发明允许帧缓冲器的有效回收,而不管接收的数据帧是存储在单个帧缓冲器还是多个帧缓冲器中。

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