公开(公告)号：US5817561A

公开(公告)日：1998-10-06

申请号：US720509

申请日：1996-09-30

申请人： Heemyong Park ,  Vida Ilderem ,  Andreas A. Wild

发明人： Heemyong Park ,  Vida Ilderem ,  Andreas A. Wild

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/2815 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/7835

摘要： An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

摘要翻译： 绝缘栅半导体器件（10）具有双间隔栅极结构（45）。 为了形成栅极结构（45），在半导体衬底（11）的主表面（12）上形成具有侧壁（22）的叠层。 然后在邻近侧壁（22）的主表面（12）上形成栅极氧化物（23）。 第一多晶硅层（24）沉积在栅极氧化物（23）和堆叠上。 蚀刻第一多晶硅层（24）以形成栅极结构（45）的第一导电间隔物（32）。 第二多晶硅层（44）沉积在第一间隔物（32）和堆叠体上。 然后蚀刻第二多晶硅层（44）以形成栅极结构（45）的第二导电间隔物（46）。 由于双重间隔栅极结构（45）不依赖于光刻技术而形成，因此其尺寸小于使用常规光刻形成的栅极结构的尺寸。

公开(公告)号：US06808974B2

公开(公告)日：2004-10-26

申请号：US09859021

申请日：2001-05-15

申请人： Heemyong Park ,  Dominic J. Schepis ,  Fariborz Assaderaghi

发明人： Heemyong Park ,  Dominic J. Schepis ,  Fariborz Assaderaghi

IPC分类号： H01L218238

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823842

摘要： A method is provided for maximizing activation of a gate electrode while preventing source and drain regions from being excessively doped. The gate electrode is partially doped when exposed the source/drain implantation step. Then, the gate electrode is fully doped by the selective implantation step while the source/drain regions are blocked. Separate annealing steps are provided subsequent to the gate doping step and the source and drain implantation step.

摘要翻译： 提供一种用于使栅电极的激活最大化同时防止源区和漏区被过度掺杂的方法。 当暴露源极/漏极注入步骤时，栅电极被部分掺杂。 然后，通过选择性注入步骤完全掺杂栅电极，同时源极/漏极区域被阻挡。 在栅极掺杂步骤和源极和漏极注入步骤之后提供单独的退火步骤。

公开(公告)号：US06627511B1

公开(公告)日：2003-09-30

申请号：US08508874

申请日：1995-07-28

申请人： Marco Racanelli ,  Hyungcheol Shin ,  Heemyong Park

发明人： Marco Racanelli ,  Hyungcheol Shin ,  Heemyong Park

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/32 ,  H01L21/76267 ,  H01L21/76275 ,  H01L21/76281

摘要： A method for forming an isolation structure (22) on a SOI substrate (11) is provided. A three layer stack of an etchant barrier layer (16), a stress relief layer (17), and an oxide mask layer (18) is formed on the SOI substrate (11). The three layer stack is patterned and etched to expose portions of the etchant barrier layer (16). The silicon layer (13) below the exposed portions of the etchant barrier layer (16) is oxidized to form the isolation structure (22). The isolation structure (22) comprises a bird's head region (21) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure (22) that leaves the SOI substrate (11) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.

摘要翻译： 提供了一种在SOI衬底（11）上形成隔离结构（22）的方法。 在SOI衬底（11）上形成蚀刻剂阻挡层（16），应力消除层（17）和氧化物掩模层（18）的三层堆叠。 图案化和蚀刻三层堆叠以暴露蚀刻剂阻挡层（16）的部分。 在蚀刻剂阻挡层（16）的暴露部分下面的硅层（13）被氧化以形成隔离结构（22）。 隔离结构（22）包括具有小的侵入的鸟头区域（21），其导致较高的边缘阈值电压。 该方法需要最小的过氧化并提供使SOI衬底（11）平坦离开的隔离结构（22）。 最小的过氧化减少了在氧化过程中形成的位错数，并且改善了器件的源漏漏。

公开(公告)号：US06566198B2

公开(公告)日：2003-05-20

申请号：US09821520

申请日：2001-03-29

申请人： Heemyong Park ,  Fariborz Assaderaghi ,  Atul C. Ajmera ,  Ghavam G. Shahidi

发明人： Heemyong Park ,  Fariborz Assaderaghi ,  Atul C. Ajmera ,  Ghavam G. Shahidi

IPC分类号： H01L21336

CPC分类号： H01L29/78696 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66772 ,  H01L29/78684

摘要： A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interface. This allows for oxide spacer formation for gate-to-source/drain isolation which makes possible raised source/drain fabrication without increasing contact resistance.

摘要翻译： 在SOI上实现CMOS结构的自对准凸起源极/漏极的CMOS结构和方法，而不依赖于硅的选择性外延生长。 在该方法中，通过进行牺牲氧化来提供CMOS结构，使得在SOI和BOX界面的表面上发生氧化。 这允许用于栅极至源极/漏极隔离的氧化物间隔物形成，这使得可能的升高的源极/漏极制造而不增加接触电阻。

公开(公告)号：US06562666B1

公开(公告)日：2003-05-13

申请号：US09702314

申请日：2000-10-31

申请人： Heemyong Park ,  Fariborz Assaderaghi ,  Jack A. Mandelman ,  Ghavam G. Shahidi ,  Lawrence F. Wagner, Jr.

发明人： Heemyong Park ,  Fariborz Assaderaghi ,  Jack A. Mandelman ,  Ghavam G. Shahidi ,  Lawrence F. Wagner, Jr.

IPC分类号： H01L2100

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device to substrate capacitance.

摘要翻译： 在SOI CMOS电路中的源极/漏极和p型衬底之间的电容通过在氧化物层下方注入n型层来减少，从而形成增加氧化物层的厚度的完全耗尽区，同时产生结电容区 这将总体器件减少到衬底电容。

公开(公告)号：US07009258B2

公开(公告)日：2006-03-07

申请号：US10753431

申请日：2004-01-09

申请人： Heemyong Park ,  Fariborz Assaderaghi ,  Jack A. Mandelman

发明人： Heemyong Park ,  Fariborz Assaderaghi ,  Jack A. Mandelman

IPC分类号： H01L21/00

CPC分类号： H01L29/78696 ,  H01L21/26506 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

摘要： The present invention provides improved controllability of the lateral etch encroachment of silicon under the spacer, in light of the fact that the exemplary method, in accordance with the present invention, comprises the step of implanting neutral ions such as Ge or Ar into the source/drain regions. The implantation creates an amorphous silicon surface, and leaves a laterally extended amorphous layer under the spacer and a well defined amorphous/crystalline interface. The etch of silicon then extends laterally underneath the spacer, due to the higher etch rate of amorphous silicon and abrupt interface between amorphous and crystalline silicon.

公开(公告)号：US06828630B2

公开(公告)日：2004-12-07

申请号：US10338103

申请日：2003-01-07

申请人： Heemyong Park ,  Byoung H. Lee ,  Paul D. Agnello ,  Dominic J. Schepis ,  Ghavam G. Shahidi

发明人： Heemyong Park ,  Byoung H. Lee ,  Paul D. Agnello ,  Dominic J. Schepis ,  Ghavam G. Shahidi

IPC分类号： H01L2976

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅电介质; 在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 以及加热所述器件以从所述注入层和所述SOI晶片形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于所述STI区域之下。

公开(公告)号：US06734109B2

公开(公告)日：2004-05-11

申请号：US09924318

申请日：2001-08-08

申请人： Heemyong Park ,  Fariborz Assaderaghi ,  Jack A. Mandelman

发明人： Heemyong Park ,  Fariborz Assaderaghi ,  Jack A. Mandelman

IPC分类号： H01L21302

CPC分类号： H01L29/78696 ,  H01L21/26506 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

摘要： The present invention provides improved controllability of the lateral etch encroachment of silicon under the spacer, in light of the fact that the exemplary method, in accordance with the present invention, comprises the step of implanting neutral ions such as Ge or Ar into the source/drain regions. The implantation creates an amorphous silicon surface, and leaves a laterally extended amorphous layer under the spacer and a well defined amorphous/crystalline interface. The etch of silicon then extends laterally underneath the spacer, due to the higher etch rate of amorphous silicon and abrupt interface between amorphous and crystalline silicon.

公开(公告)号：US06097060A

公开(公告)日：2000-08-01

申请号：US99807

申请日：1998-06-18

申请人： Heemyong Park ,  Vida Ilderem ,  Andreas A. Wild

发明人： Heemyong Park ,  Vida Ilderem ,  Andreas A. Wild

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/49

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/2815 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/7835

摘要： An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

摘要翻译： 绝缘栅半导体器件（10）具有双间隔栅极结构（45）。 为了形成栅极结构（45），在半导体衬底（11）的主表面（12）上形成具有侧壁（22）的叠层。 然后在邻近侧壁（22）的主表面（12）上形成栅极氧化物（23）。 第一多晶硅层（24）沉积在栅极氧化物（23）和堆叠上。 蚀刻第一多晶硅层（24）以形成栅极结构（45）的第一导电间隔物（32）。 第二多晶硅层（44）沉积在第一间隔物（32）和堆叠体上。 然后蚀刻第二多晶硅层（44）以形成栅极结构（45）的第二导电间隔物（46）。 由于双重间隔栅极结构（45）不依赖于光刻技术而形成，因此其尺寸小于使用常规光刻形成的栅极结构的尺寸。

公开(公告)号：US5879999A

公开(公告)日：1999-03-09

申请号：US720510

申请日：1996-09-30

申请人： Heemyong Park ,  Vida Ilderem ,  Robert B. Davies

发明人： Heemyong Park ,  Vida Ilderem ,  Robert B. Davies

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/2815 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/7836

摘要： An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate dielectric (23) is then formed over the major surface (12) adjacent to the sidewalls (22). The conductive spacer (32) is formed on the gate dielectric (23). The extension region (46) is then formed using selective growth or deposition and patterning of polysilicon adjacent the conductive spacer (32).

摘要翻译： 一种具有栅极结构（45）的绝缘栅极半导体器件（10），其包括导电间隔物（32）和从导电间隔物（32）延伸的延伸区域（46）。 为了形成栅极结构（45），在半导体衬底（11）的主表面（12）上形成具有侧壁（22）的叠层。 然后在与侧壁（22）相邻的主表面（12）上形成栅极电介质（23）。 导电间隔物（32）形成在栅极电介质（23）上。 然后使用与导电间隔物（32）相邻的多晶硅的选择性生长或沉积和图案化形成延伸区（46）。