公开(公告)号：US6040736A

公开(公告)日：2000-03-21

申请号：US984959

申请日：1997-12-04

Applicant: Andrea Milanesi ,  Vanni Poletto ,  Alberto Poma ,  Marco Morelli

Inventor： Andrea Milanesi ,  Vanni Poletto ,  Alberto Poma ,  Marco Morelli

IPC: G05F1/575 ,  G05F1/10

CPC classification number: G05F1/575

Abstract: A voltage-regulator circuit with a low voltage drop uses a DMOS power transistor driven by a charge pump. The control circuit includes two feedback loops: a first feedback loop having a high gain and accuracy but low response speed, and a second feedback loop having a wide passband and fast response speed, but low gain.

Abstract translation: 具有低压降的电压调节器电路使用由电荷泵驱动的DMOS功率晶体管。 控制电路包括两个反馈回路：具有高增益和精度但低响应速度的第一反馈回路，以及具有宽通带和快速响应速度但低增益的第二反馈回路。

公开(公告)号：US6040734A

公开(公告)日：2000-03-21

申请号：US109630

申请日：1998-07-02

Applicant: Corrado Villa ,  Luigi Bettini ,  Simone Bartoli

Inventor： Corrado Villa ,  Luigi Bettini ,  Simone Bartoli

IPC: G11C5/14 ,  G11C16/12 ,  H03K17/687 ,  H03K17/693 ,  H02J3/38

CPC classification number: G11C5/143 ,  G11C16/12 ,  H03K17/6871 ,  H03K17/693

Abstract: A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors connected in series provides that at least one branch of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first and a second pairs of transistors connected between a first supply voltage reference and a common node. The first pair comprises transistors bigger than the transistors of the second pair while between the transistors making up the second pair is inserted a pair of resistors. Between the pair of resistors there is an interconnection node connected to a corresponding interconnection node between the transistors of the first pair.

Abstract translation: 用于在电源电压之间切换的电路，特别是用于非易失性闪速存储器件的电路以及包括第一和第二电路支路的类型的电路，每个连接在一起的串联的一对晶体管使电路的至少一个支路与 由P沟道MOS晶体管构成的桥接电路。 该桥由连接在第一电源电压基准和公共节点之间的第一对和第二对晶体管构成。 第一对包括大于第二对的晶体管的晶体管，而构成第二对的晶体管之间插入一对电阻器。 在一对电阻器之间存在连接到第一对晶体管之间的对应互连节点的互连节点。

公开(公告)号：US6040730A

公开(公告)日：2000-03-21

申请号：US98740

申请日：1993-07-28

Applicant: Bruno Ferrario

Inventor： Bruno Ferrario

IPC: H03H11/46 ,  G06G7/62 ,  G11C27/02 ,  G06G7/64 ,  H03B1/00

CPC classification number: G11C27/026 ,  G06G7/62 ,  H03H11/483

Abstract: An integrated capacitance multiplier circuit utilizes a pair of field effect transistors, biased in a conducting state, as virtual resistances of a classic operational amplifier network for implementing a capacitance multiplier function. The two field effect transistors have different sizes from each other for attaining a given ON-resistance ratio. A biasing circuit provides independently adjustable biasing voltages for the two field effect transistors. At least one of the two biasing voltages produced by the biasing circuit can be made dependent on temperature according to a certain dependency law in order to exploit the capacitance multiplier circuit for temperature compensating an integrated RC circuit employing the virtual capacitance provided by the multiplier circuit.

Abstract translation: 集成电容倍增器电路利用一对场效应晶体管，其被置于导通状态，作为用于实现电容倍增器功能的经典运算放大器网络的虚拟电阻。 两个场效应晶体管具有彼此不同的尺寸以获得给定的导通电阻比。 偏置电路为两个场效应晶体管提供可独立调节的偏置电压。 由偏置电路产生的两个偏置电压中的至少一个可以根据某种依赖规律取决于温度，以便利用采用由乘法电路提供的虚拟电容的集成RC电路进行温度补偿的电容乘法器电路。

公开(公告)号：US6023295A

公开(公告)日：2000-02-08

申请号：US926352

申请日：1997-09-09

Applicant: Danilo Pau

Inventor： Danilo Pau

IPC: G06T9/00 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50

CPC classification number: H04N19/428 ,  H04N19/124 ,  H04N19/423 ,  H04N19/50 ,  H04N19/61

Abstract: The video memory requirement of an MPEG decoder, or of an SQTV processor, or of similar devices, wherein the storing of full pages or pixels or portions thereof is performed in decoding or in filtering noise, may be dynamically reduced by ADPCM recompressing and decompressing of the MPEG decoded digital data stream, before and after storing the data in the video memory, respectively. A particularly efficient and simple ADPCM compression method employs a differential variance estimator which, instead of processing bidimensional blocks of pels, instead processes blocks of pels all belonging to a same horizontal video line.

Abstract translation: MPEG解码器或SQTV处理器或类似设备的视频存储器要求可以通过ADPCM再压缩和解压缩来动态地减少，其中在解码或滤波噪声中执行全页或像素或其部分的存储 MPEG解码数字数据流，分别在数据存储在视频存储器中之前和之后。 特别有效和简单的ADPCM压缩方法采用差分方差估计器，其不是处理像素的二维块，而是处理所有属于相同水平视频行的像素块。

公开(公告)号：US6002542A

公开(公告)日：1999-12-14

申请号：US904599

申请日：1997-08-01

Applicant: Melchiorre Bruccoleri ,  Marco Demicheli ,  Davide Demicheli ,  Giuseppe Patti

Inventor： Melchiorre Bruccoleri ,  Marco Demicheli ,  Davide Demicheli ,  Giuseppe Patti

IPC: G11B5/55 ,  G11B5/596 ,  G11B21/10

CPC classification number: G11B5/59688 ,  G11B5/59605 ,  G11B5/5534

Abstract: A servo-demodulator for a pair of alternating signals generated by a magnetic disc read head and indicative of the position of the read head in relation to the center of a recorded track. The servo-demodulator comprises a peak detector for successively and individually sampling the amplitude of each of a plurality of peaks of the pair of alternating signals, and a capacitor periodically connected to the output of the peak detector by a control logic for deriving a weighted average of the various successively sampled amplitudes. In this manner, the control logic obtains an averaged measure of amplitude with high immunity to noise.

Abstract translation: 一种用于由磁盘读取头产生的一对交替信号的伺服解调器，并且指示读取头相对于记录轨道的中心的位置。 伺服解调器包括峰值检测器，用于连续和单独地采样该对交变信号的多个峰值中的每一个的振幅;以及电容器，通过用于导出加权平均值的控制逻辑周期性地连接到峰值检测器的输出端 的各种连续采样幅度。 以这种方式，控制逻辑获得具有高抗噪声能力的幅度的平均测量值。

公开(公告)号：US5985718A

公开(公告)日：1999-11-16

申请号：US996922

申请日：1997-12-23

Applicant: Giovanna Dalla Libera ,  Bruno Vajana ,  Roberta Bottini ,  Carlo Cremonesi

Inventor： Giovanna Dalla Libera ,  Bruno Vajana ,  Roberta Bottini ,  Carlo Cremonesi

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/66825

Abstract: A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer. A capacitive implant mask having a window is formed by depositing a layer of a light-sensitive material over the additional polysilicon layer, a dopant is implanted through the window at an energy and with dosages effective to penetrate the polycrystalline silicon, ONO, and polysilicon layers, respectively, and a region of electric continuity is formed laterally and beneath the thin tunnel oxide region.

Abstract translation: 一种用于制造具有两级多晶硅并且被包括在EEPROM类型的存储器件中的存储单元的工艺，其中该器件形成在具有第一导电类型的半导体材料衬底上。 该方法包括以下步骤：在衬底上形成由先前形成在同一衬底上的栅极氧化物区域围绕的薄的隧道氧化物区域，在栅极氧化物区域和薄的隧道氧化物区域上沉积多晶硅层，并依次沉积 多晶硅层上的复合ONO层和附加多晶硅层。 具有窗口的电容注入掩模通过在附加多晶硅层上沉积感光材料层而形成，通过窗口以能量注入掺杂剂并且具有有效穿透多晶硅，ONO和多晶硅层的剂量 并且在薄隧道氧化物区域的横向和下方形成电连续性区域。

公开(公告)号：US5970785A

公开(公告)日：1999-10-26

申请号：US853163

申请日：1997-05-08

Applicant: Valerio Giorgetta ,  Paolo Mastella ,  Giampietro Maggioni ,  Mirco Contucci

Inventor： Valerio Giorgetta ,  Paolo Mastella ,  Giampietro Maggioni ,  Mirco Contucci

IPC: F02D41/14 ,  G01M15/00

CPC classification number: F02D41/1494

Abstract: A circuit comprises a measurement resistor in series with a heater, a detector circuit for providing a signal indicative of the current flowing in the resistor, switching devices for controlling the connection of the heater to a voltage source and the connection of the measurement resistor in the supply circuit comprising the source and the heater, and a control unit arranged to drive the switching devices in a manner such that each time the heater is activated, the measurement resistor is kept disconnected from the supply circuit of the heater for a predetermined period of time and the measurement resistor is then connected in the supply circuit of the heater.

Abstract translation: 电路包括与加热器串联的测量电阻器，用于提供指示在电阻器中流动的电流的信号的检测器电路，用于控制加热器与电压源的连接的开关装置以及测量电阻器的连接 包括源极和加热器的电源电路以及控制单元，其被布置成以每次加热器被激活的方式驱动开关装置，测量电阻器与加热器的电源电路保持断开预定的时间段 然后将测量电阻连接在加热器的供电电路中。

公开(公告)号：US5968183A

公开(公告)日：1999-10-19

申请号：US868214

申请日：1997-06-03

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C29/00 ,  G06F11/00

CPC classification number: G11C29/80 ,  G11C29/808

Abstract: A semiconductor memory device includes: a plurality of output data terminals; a matrix of memory cells including a plurality of groups of columns of memory cells, each group of columns being associated with a respective output data terminal; column selection means associated with the matrix of memory cells for selectively coupling one column for each of the group of columns to a respective sensing means driving the output data terminal; redundancy columns of redundancy memory cells for functionally replacing defective columns in the matrix; redundancy column selection means associated with the redundancy columns for selectively coupling one redundancy column to a redundancy sensing means; defective address storage means for storing defective addresses of the defective columns and identifying codes suitable for identifying the groups of columns wherein the defective columns are located, for comparing the defective addresses with a current address supplied to the memory device and for driving the redundancy column selection means for selecting a redundancy column when a current address supplied to the memory device coincides with one of the defective addresses. A shared bus including a plurality of signal lines is provided in the memory device for interconnecting a plurality of circuit blocks of the memory device and for transferring signals between the circuit blocks, the shared bus being selectively assignable to the circuit blocks in prescribed respective time intervals. The memory device also includes first bus assignment means associated with the defective address storage means and second bus assignment means associated with the sensing means.

Abstract translation: 半导体存储器件包括：多个输出数据端子; 存储器单元的矩阵，包括多组存储器单元的列，每组列与相应的输出数据端相关联; 与存储器单元的矩阵相关联的列选择装置，用于选择性地将一组列中的每一列耦合到驱动输出数据端的相应检测装置; 冗余存储单元的冗余列，用于功能性地替换矩阵中的有缺陷的列; 与冗余列相关联的冗余列选择装置，用于选择性地将一个冗余列耦合到冗余感测装置; 用于存储缺陷列的缺陷地址的缺陷地址存储装置和用于识别缺陷列所在的列组的识别码，用于将缺陷地址与提供给存储装置的当前地址进行比较，并用于驱动冗余列选择 当提供给存储装置的当前地址与缺陷地址之一一致时用于选择冗余列的装置。 包括多个信号线的共享总线被提供在存储器装置中，用于互连存储器件的多个电路块，并用于在电路块之间传送信号，共享总线可以规定的各个时间间隔选择性地分配给电路块 。 存储装置还包括与缺陷地址存储装置相关联的第一总线分配装置和与感测装置相关联的第二总线分配装置。

公开(公告)号：US5963065A

公开(公告)日：1999-10-05

申请号：US787301

申请日：1997-01-24

Applicant: Roberto Alini ,  Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Valerio Pisati

Inventor： Roberto Alini ,  Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Valerio Pisati

IPC: H03F3/30 ,  H03F3/34 ,  H03F3/26

CPC classification number: H03F3/3077

Abstract: A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).

Abstract translation: 低失调放大器具有由推挽装置中的npn晶体管和pnp晶体管构成的输出级和驱动级。 后者包括电流镜电路，其在其输入支路中具有与第一恒定电流发生器串联的pnp晶体管，并且在其输出支路中具有npn晶体管，以及两个互补双极晶体管，其中集电极连接到输出端 端子和基极连接到放大器的输入端子。 驱动器级的pnp晶体管的发射极通过第二恒流发生器连接到电源的正极端子，并连接到输出级的npn晶体管的基极，驱动器级的npn晶体管的发射极 通过电流镜电路的输出支路的npn晶体管和输出级的pnp晶体管的基极连接到电源的负极。 放大器具有非常低或零偏移（Vos = Vout-Vin）。

公开(公告)号：US5959476A

公开(公告)日：1999-09-28

申请号：US828791

申请日：1997-03-27

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C5/14 ,  H03K17/22 ,  H03L7/00

CPC classification number: G11C5/143 ,  H03K17/223

Abstract: The circuit, integrated in a device, includes a generating stage generating a POR pulse and a bump detector detecting bump conditions on the common supply line and enabling the generating stage in the presence of a bump. A bump supply line is connected to a holding capacitor and to the common supply line via an isolation stage. The isolation stage connects the common supply line and the bump supply line in the absence of a bump, and isolates the bump supply line in the presence of a bump. The bump detector is connected to the common supply line and to the bump supply line to generate the POR pulse when the common supply line falls beyond a given level below the voltage of the bump supply line. The circuit is also used to generate a POR pulse in the presence of a low supply voltage and when the device is turned off, to ensure correct operation of the device.

Abstract translation: 集成在器件中的电路包括产生POR脉冲的发生级和用于检测公共电源线上的突起状况的凸块检测器，并且在存在凸块的情况下使得能够产生发电级。 凸块供电线通过隔离级连接到保持电容器和公共电源线。 隔离级在没有凸块的情况下连接公共电源线和凸块供电线，并且在存在凸块的情况下隔离凸块供电线。 当公共电源线超过低于凸块供电线电压的给定电平时，凸块检测器连接到公共电源线和凸块供电线以产生POR脉冲。 该电路还用于在存在低电源电压和器件关闭时产生POR脉冲，以确保器件的正常工作。