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公开(公告)号：US20220382695A1
公开(公告)日：2022-12-01
申请号：US17747800
申请日：2022-05-18
发明人： Rolf Nandlinger , Roberto Colombo
摘要： In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.
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公开(公告)号：US20220334862A1
公开(公告)日：2022-10-20
申请号：US17235206
申请日：2021-04-20
摘要： Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.
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公开(公告)号：US20220308892A1
公开(公告)日：2022-09-29
申请号：US17654537
申请日：2022-03-11
IPC分类号： G06F9/4401 , G06F9/30
摘要： In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
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公开(公告)号：US20220159807A1
公开(公告)日：2022-05-19
申请号：US17523641
申请日：2021-11-10
申请人： STMicroelectronics S.r.l. , STMicroelectronics Application GmbH , STMicroelectronics Design and Application S.R.O.
发明人： Donato TAGLIAVIA , Vincenzo POLISI , Calogero Andrea TRECARICHI , Francesco Nino MAMMOLITI , Jochen BARTHEL , Ludek BERAN
摘要： A control circuit for a voltage source generates a reference signal for a voltage source, wherein the reference signal indicates a requested output voltage to be generated by the voltage source. A digital feed-forward control circuit computes a digital feed-forward regulation value indicative of a requested output voltage by determining a maximum voltage drop at strings of solid-state light sources. A digital feed-back control circuit determines a minimum voltage drop for current regulators/limiters for the strings and determines a digital feed-back correction value as a function of the minimum voltage drop. The control circuit then sets the reference signal after a start-up as a function of the digital feed-forward regulation value and corrects the reference signal as a function of the digital feed-back correction value.
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公开(公告)号：US20220137128A1
公开(公告)日：2022-05-05
申请号：US17083876
申请日：2020-10-29
申请人： STMicroelectronics International N.V. , STMicroelectronics Application GmbH , STMicroelectronics S.r.l.
IPC分类号： G01R31/317 , G01R31/3185
摘要： A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.
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公开(公告)号：US20220018907A1
公开(公告)日：2022-01-20
申请号：US17368198
申请日：2021-07-06
发明人： Markus Ekler
IPC分类号： G01R31/382 , G01R31/396 , G01R31/367 , B60L58/12 , H01M10/42
摘要： An embodiment processing system comprises terminals configured to be connected to cells of a rechargeable battery to receive cell voltages, a digital processing circuit, a serial communication interface and a transmission queue interfacing the digital processing circuit with the serial communication interface for parallel operation. The digital processing circuit synchronously acquires a given number of digital samples of each of the cell voltages and stores them to a memory. The digital processing circuit encodes the digital samples stored to the memory via a data compression module, and stores the encoded data to the transmission queue. For example, the data compression module may generate the encoded data by subtracting a given offset from each digital sample to generate values indicative of the dynamic variation of each sample with respect to the offset, and removing a given number of most significant bits from each value.
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公开(公告)号：US20210384852A1
公开(公告)日：2021-12-09
申请号：US17323602
申请日：2021-05-18
申请人： STMicroelectronics S.r.l. , STMicroelectronics Application GMBH , STMicroelectronics (Alps) SAS
IPC分类号： H02P7/03 , H02P7/29 , H03K3/037 , H03K17/687 , E05F15/60
摘要： An embodiment driver circuit comprises a power supply pin configured to receive a power supply voltage, and a set of control pins configured to provide a set of control signals for controlling switching of a set of switches of an h-bridge circuit comprising a pair of high-side switches and a pair of low-side switches. The driver circuit comprises control circuitry coupled to the control pins and configured to generate the control signals, and sensing circuitry coupled to the power supply pin and configured to generate a detection signal indicative of the power supply voltage exceeding a threshold value. The control circuitry is sensitive to the detection signal and is configured to generate the control signals to activate one of the pair of high-side switches and the pair of low-side switches and de-activate the other of the pair of high-side switches and the pair of low-side switches.
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公开(公告)号：US20210357344A1
公开(公告)日：2021-11-18
申请号：US17245894
申请日：2021-04-30
发明人： Fred Rennig , Vaclav Dvorak , Ludek Beran
IPC分类号： G06F13/362 , H04L12/40 , G06F11/07
摘要： An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.
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公开(公告)号：US20210303504A1
公开(公告)日：2021-09-30
申请号：US17199418
申请日：2021-03-11
发明人： Rolf Nandlinger , Radek Olexa
摘要： An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.
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公开(公告)号：US20210281497A1
公开(公告)日：2021-09-09
申请号：US17182914
申请日：2021-02-23
发明人： Fred Rennig
IPC分类号： H04L12/26
摘要： In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.
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