公开(公告)号：US20140215060A1

公开(公告)日：2014-07-31

申请号：US14157948

申请日：2014-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdok MO ,  Sungmin LEE

IPC: H04L12/26

CPC classification number: H04L41/082 ,  G06F8/76 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/44 ,  G06F9/455 ,  G06F11/1402 ,  G06F11/1433 ,  H04L43/0894

Abstract: A software migration method and an apparatus for migration of software running at a source node to a destination node with a migration scheme selected optimally in consideration of micro-server communication environment are provided. The software migration apparatus includes an environment monitor which monitors communication environment between a source node and a destination node constituting a micro-server and a migration policy manager which analyzes communication environment information acquired from the environment monitor and determines a migration scheme for migrating a software running at the source node to the destination node based on the analysis result.

Abstract translation: 提供了一种考虑到微服务器通信环境，优选地选择在源节点处运行的软件迁移到具有迁移方案的目的地节点的软件迁移方法和装置。 软件迁移装置包括监视源节点与构成微服务器的目的地节点之间的通信环境的环境监视器以及分析从环境监视器获取的通信环境信息的迁移策略管理器，并且确定用于迁移正在运行的软件的迁移方案 在源节点根据分析结果到目标节点。

公开(公告)号：US20120011345A1

公开(公告)日：2012-01-12

申请号：US13178961

申请日：2011-07-08

Applicant: Ian Robertson ,  Roger Paul Bowman ,  Robert Henderson Wood

Inventor： Ian Robertson ,  Roger Paul Bowman ,  Robert Henderson Wood

IPC: G06F15/76 ,  G06F9/06

CPC classification number: G06F21/72 ,  G06F9/22 ,  G06F17/30477 ,  G06F21/73 ,  G06F21/88 ,  G06F2221/2103 ,  G06F2221/2107 ,  G06F2221/2111 ,  H04W12/12

Abstract: Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a message from a service, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, extended functionality may be realized.

Abstract translation: 扩展处理器硬件包含一个微码解释器。 当加密的微码被包括在来自服务的消息中时，微码可以传递给微码解释器。 基于在处理器硬件处发生的微代码的解密和执行，可以实现扩展功能。

公开(公告)号：US20110219207A1

公开(公告)日：2011-09-08

申请号：US12987391

申请日：2011-01-10

Applicant: Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

Inventor： Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

IPC: G06F15/76 ,  G06F9/22

CPC classification number: G06F9/22 ,  G06F15/76 ,  G06F15/7867

Abstract: A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.

Abstract translation: 提供了一种用于有效执行向量操作的可重构处理器，以及一种控制可重构处理器的方法。 可重配置处理器基于向量车道配​​置信息将多个处理元件中的至少一个指定为向量车道，并且向指定的向量车道分配向量操作。

公开(公告)号：US07941644B2

公开(公告)日：2011-05-10

申请号：US12252541

申请日：2008-10-16

Applicant: Eric Oliver Mejdrich ,  Adam James Muff ,  Matthew Ray Tubbs

Inventor： Eric Oliver Mejdrich ,  Adam James Muff ,  Matthew Ray Tubbs

IPC: G06F9/46

CPC classification number: G06F9/3885 ,  G06F9/22 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3867

Abstract: A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer logic issues a plurality of instructions associated with a long latency operation to one execution unit, while blocking instructions from the instruction buffer logic from being issued to that execution unit. In addition, the blocking of instructions from being issued to the execution unit does not affect the issuance of instructions to any other execution unit, and as such, other instructions from the instruction buffer logic are still capable of being issued to and executed by other execution units even while the sequencer logic is issuing the plurality of instructions associated with the long latency operation.

Abstract translation: 处理单元包括多个执行单元和定序器逻辑，其布置在指令缓冲器逻辑的下游，并且响应于指令流中存在的定序器指令。 响应于这样的指令，定序器逻辑向一个执行单元发出与长等待时间操作相关联的多个指令，同时阻止来自指令缓冲器逻辑的指令被发布到该执行单元。 此外，指令的阻塞被发布到执行单元不影响向任何其他执行单元发出指令，因此来自指令缓冲器逻辑的其他指令仍然能够被发出并由其他执行执行 即使当定序器逻辑发出与长延迟操作相关联的多个指令时。

公开(公告)号：US06742107B2

公开(公告)日：2004-05-25

申请号：US09782285

申请日：2001-02-14

Applicant: Akira Jinzaki

Inventor： Akira Jinzaki

IPC: G06F1582

CPC classification number: G06F9/3001 ,  G06F9/22 ,  G06F9/30145

Abstract: A table storing a state transition rule is arranged in a memory. By referencing the table based on input data, the process to be performed for the input data is determined and executed. Additionally, a process capability can be changed by altering a setting in this table. As a result, a data processing device that can perform the processes for general-purpose data, such as a stream data process, etc., at high speed, and can flexibly change a capability according to the circumstances.

Abstract translation: 存储状态转移规则的表被布置在存储器中。 通过基于输入数据引用表，确定并执行要对输入数据执行的处理。 此外，可以通过更改此表中的设置来更改流程功能。 结果，能够高速地进行流数据处理等通用数据处理的数据处理装置，能够根据情况灵活地变更能力。

公开(公告)号：US4835738A

公开(公告)日：1989-05-30

申请号：US846673

申请日：1986-03-31

Applicant: Jeffrey A. Niehaus ,  John W. Kronlage

Inventor： Jeffrey A. Niehaus ,  John W. Kronlage

IPC: G06F9/22

CPC classification number: G06F9/22

Abstract: A microsequencer includes a memory array (110) which is interfaced with a push/pop register (100). Data is input to the push/pop register (100) through a multiplexer (104) and also to Read register (102). The stack comprised of the RAM (110) and the register (100) can be push or pop with control logic (120). Stack pointer (130) and Read pointer (134) are provided for storing the stack and read pointers. The Read register (102) allows reading of data independent of the contents of the push/pop register (100) and the Read pointer (134) allows independent reading of information in the RAM (110).

Abstract translation: 微定序器包括与推/放寄存器（100）接口的存储器阵列（110）。 数据通过多路复用器（104）和读寄存器（102）输入到推/弹寄存器（100）。 由RAM（110）和寄存器（100）组成的堆叠可以通过控制逻辑（120）进行推送或弹出。 堆栈指针（130）和读指针（134）用于存储堆栈和读指针。 读寄存器（102）允许独立于推/弹寄存器（100）的内容读取数据，并且读指针（134）允许RAM（110）中的信息的独立读取。

公开(公告)号：US3700873A

公开(公告)日：1972-10-24

申请号：US3700873D

申请日：1970-04-06

Applicant: IBM

Inventor： YHAP ERNESTO F

IPC: G06F9/22 ,  G06F7/38

CPC classification number: G06F9/22

Abstract: An idealized language notation is disclosed for a computer system whereby both data and instructions may be logically combined and operated upon utilizing a set of micro-instructions which have desirable algebraic qualities for this structural concept of a computer language and an embodiment is given of a structured computer architecture. This set of micro-instructions lends itself to simple hardware realizations requiring minimal levels of logic. The nature of the hardware is highly amenable to realization with large scale integration techniques and should facilitate the emulation of a wide set of more specific machine language instructions. The disclosed hardware while simple is capable of decoding and performing a relatively large number of primitive logical operations, which operations are representative of the particular micro-program which originated same and which micro-programs are further combinable to perform all normal machine operations.

Abstract translation: 公开了一种用于计算机系统的理想化语言符号，由此数据和指令可以在逻辑上组合并且在利用对于计算机语言的该结构概念具有期望的代数性质的微指令的集合来操作，并且实施例被给予结构化 电脑架构。 这组微指令本身就需要最低限度逻辑的简单硬件实现。 硬件的性质非常适合用大规模集成技术来实现，并且应该有助于仿真更广泛的更具体的机器语言指令。

公开(公告)号：US20240257107A1

公开(公告)日：2024-08-01

申请号：US18407419

申请日：2024-01-08

Applicant: nChain Licensing AG

Inventor： Craig Steven WRIGHT ,  Stephane SAVANAH

IPC: G06Q20/36 ,  G06F9/22 ,  G06F9/30 ,  G06F21/60 ,  G06F21/62 ,  G06Q20/38 ,  H04L9/00 ,  H04L9/06 ,  H04L9/30 ,  H04L9/32

CPC classification number: G06Q20/3678 ,  G06F9/22 ,  G06F9/30021 ,  G06F9/30029 ,  G06F21/602 ,  G06F21/6218 ,  G06Q20/3827 ,  G06Q20/3829 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/3066 ,  H04L9/321 ,  H04L9/3239 ,  H04L9/3242 ,  H04L9/3252 ,  G06F21/6236 ,  H04L9/50 ,  H04L2209/56

Abstract: Techniques are provided to implement the functionality of a logic gate by blockchain transaction. A method includes providing a locking script in a first transaction, comprising an instruction to process Boolean input; providing a further transaction having an unlocking script; processing an input signal to provide a Boolean input; and using the Boolean input to execute the locking and unlocking scripts of the first and further transactions, wherein the computing resource or agent influence the behaviour of a device or process based upon the validity of the further transaction; transmitting the further transaction and/or first transaction to a blockchain network for validation; interpreting the detecting of the further transaction within the blockchain or blockchain network as the TRUE output of a logic gate; and interpreting the failure to detect the further transaction within the blockchain or blockchain network as the FALSE output of the logic gate.

公开(公告)号：US20240053983A1

公开(公告)日：2024-02-15

申请号：US18220536

申请日：2023-07-11

Applicant: Google LLC

Inventor： Jonathan Charles Masters

IPC: G06F9/22 ,  G06F9/38

CPC classification number: G06F9/22 ,  G06F9/3844

Abstract: Aspects of the technology are directed to methods and systems that enable duplication of micro-architectural context information when a running application is cloned (e.g., for a faster function start up), migrated (e.g., to another core or machine), or persisted into secondary storage. The method, for example, may comprise extracting microarchitectural information from a first processing element, transferring the extracted microarchitectural information to a first operating system, forwarding, by the first operating system, the extracted microarchitectural information to a second processing element, and instantiating a process at the second processing element using the extracted microarchitectural information.

公开(公告)号：US11694193B2

公开(公告)日：2023-07-04

申请号：US16097516

申请日：2017-04-28

Applicant: nChain Licensing AG

Inventor： Craig Steven Wright ,  Stephane Savanah

IPC: G06Q20/36 ,  G06Q20/38 ,  H04L9/30 ,  H04L9/32 ,  G06F9/30 ,  G06F21/62 ,  G06F21/60 ,  G06F9/22 ,  H04L9/06 ,  H04L9/00

CPC classification number: G06Q20/3678 ,  G06F9/22 ,  G06F9/30021 ,  G06F9/30029 ,  G06F21/602 ,  G06F21/6218 ,  G06Q20/3827 ,  G06Q20/3829 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/3066 ,  H04L9/321 ,  H04L9/3239 ,  H04L9/3242 ,  H04L9/3252 ,  G06F21/6236 ,  H04L9/50 ,  H04L2209/56

Abstract: The invention presents a solution in which blockchain Transactions are created to implement the functionality of a logic gate. The invention may be implemented on the Bitcoin platform or an alternative blockchain platform. The transaction includes a locking script which comprises instructions selected so as to implement the functionality of a logic gate, such as the XOR gate. When the script is executed (because a second transaction is attempting to spend the output associated with the locking script) the inputs will be processed by the conditional instructions to provide an output of TRUE or FALSE. The inputs are pre-processed by one or more computing agents so that they are evaluated to TRUE or FASLE prior to being used as inputs to the script. The second transaction is transmitted to the blockchain network for validation and, if determined to be valid, it will be written to the blockchain. Validation of the second transaction can be interpreted as a TRUE output. Thus, the locking script of the first transaction provides the functionality of the desired logic gate. The invention provides numerous advantages and can be used in a wide variety of applications, such as for the implementation of control systems and unit.