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公开(公告)号：US3581213A
公开(公告)日：1971-05-25
申请号：US3581213D
申请日：1968-05-09
Applicant: ELMO E CRUMP
Inventor： CRUMP ELMO E
Abstract: A burst generator including a continuous wave oscillator, means to synchronize a pulse generator to the oscillator so that each pulse starts at a corresponding point on a cycle of the continuous wave, and a gating circuit actuated by the pulses to transmit repetitive bursts of oscillations, each starting at a corresponding point of a cycle.
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公开(公告)号：US10298214B2
公开(公告)日：2019-05-21
申请号：US15584448
申请日：2017-05-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye-Won Shim , Dong-Uk Park , Phil-Jae Jeon , Sang-Woo Pae , Da Ahn
Abstract: A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.
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公开(公告)号：US09876486B2
公开(公告)日：2018-01-23
申请号：US15464600
申请日：2017-03-21
Applicant: MARVELL WORLD TRADE LTD.
Inventor： Gideon Paul
IPC: H03K3/356 , H03K3/012 , H03K3/3562 , H03K3/66 , H03K5/24
CPC classification number: H03K3/012 , H03K3/356121 , H03K3/35625 , H03K3/66 , H03K5/24
Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.
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公开(公告)号：US06911874B2
公开(公告)日：2005-06-28
申请号：US10067025
申请日：2002-02-04
Applicant: Mark Daniel Dvorak
Inventor： Mark Daniel Dvorak
CPC classification number: H04B1/7174 , H03K7/04
Abstract: A modulated ultra wideband pulse generation system is provided. The system comprises a pulse waveform generator circuit operable to generate an on-off pulse waveform, and a modulating circuit operable to receive a modulating signal and to modulate the on-off pulse waveform in response to the modulating signal. Further embodiments of the invention comprise a variable bandwidth circuit operable to alter the bandwidth of the pulses comprising the on-off pulse waveform. Various embodiments of the invention comprise on-off keying modulation, pulse position modulation, and pulse phase modulation.
Abstract translation: 提供调制超宽带脉冲发生系统。 该系统包括可操作以产生开关脉冲波形的脉冲波形发生器电路，以及可操作以接收调制信号并响应于调制信号调制开 - 关脉冲波形的调制电路。 本发明的另外的实施例包括可变带宽电路，其可操作以改变包括开 - 关脉冲波形的脉冲的带宽。 本发明的各种实施例包括开关键控调制，脉冲位置调制和脉冲相位调制。
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公开(公告)号：US5434523A
公开(公告)日：1995-07-18
申请号：US223186
申请日：1994-04-05
Applicant: Ray D. Sundstrom
Inventor： Ray D. Sundstrom
CPC classification number: H03K5/1565 , H03K9/08
Abstract: The present invention provides an output signal whose pulse width may be adjusted with respect to the pulse width of an incoming input signal. In particular, a plurality of signals is generated in response to the input signal. One of the plurality of signals is selected for controlling when the output signal transitions from a first logic state to a second logic state, and one of the plurality of signals is selected for controlling when the output signal transitions from a second logic state to a first logic state wherein the output signal has a pulse width being a function of the selection of the plurality of signals.
Abstract translation: 本发明提供一种输出信号，其脉冲宽度可以相对于输入输入信号的脉冲宽度进行调节。 特别地，响应于输入信号产生多个信号。 选择多个信号中的一个用于控制何时输出信号从第一逻辑状态转换到第二逻辑状态，并且选择多个信号中的一个用于控制何时输出信号从第二逻辑状态转换到第一逻辑状态 逻辑状态，其中所述输出信号具有作为所述多个信号的选择的函数的脉冲宽度。
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Patent Agency Ranking
公开(公告)号：US4401977A
公开(公告)日：1983-08-30
申请号：US222942
申请日：1981-01-06
Applicant: Derek R. Taylor
Inventor： Derek R. Taylor
CPC classification number: G07C9/00111 , H04B1/04
Abstract: This radio transmitter is for use in an access control system and comprises a hands-free pocket token arranged to transmit bursts of oscillations at a preset carrier frequency with a preset number of carrier frequency cycles in each burst. The transmitter is controlled by a logic circuit driven from a counter of the number of oscillations both in a transmission burst and in the interval between bursts, so that a particularly simple system is provided which can be easily reset in accordance with requirements.
Abstract translation: 该无线电发射机用于访问控制系统，并且包括免提口袋令牌，其设置成以预设载波频率以每个突发中的预设数量的载波频率周期传送脉冲串。 发射机由在传输脉冲串和脉冲串之间的间隔中的振荡次数的计数器驱动的逻辑电路控制，使得提供可以根据需要容易地复位的特别简单的系统。
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17.发明授权Coaxial line reed switch fast rise signal generator with attenuation means forming outer section of the line 失效同轴线路开关快速上升信号发生器，具有衰减手段，形成线路外部
公开(公告)号：US3564277A
公开(公告)日：1971-02-16
申请号：US3564277D
申请日：1969-08-25
Applicant: SPERRY RAND CORP
Inventor： MAGUIRE HUGH C
CPC classification number: H01P1/125
Abstract: A hollow cylinder of electromagnetic energy-absorbing material forms a portion of the outer conductor of a coaxial transmission line, the portion encompassing a mercury-wetted, magnetic field operated, reed switch that joins center conductor portions of input and output coaxial lines. When actuated by an externally generated magnetic field, the reed switch is operated to cause a relatively undistorted, sharp voltage step signal to flow along the output coaxial line.
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公开(公告)号：US10483951B2
公开(公告)日：2019-11-19
申请号：US15693440
申请日：2017-08-31
Applicant: Altera Corporation
Inventor： Nelson Gaspard , Yanzhong Xu
IPC: H03K3/66 , G11C11/00 , G11C29/50 , G11C11/419 , H03B5/12 , H03K3/013 , H03K3/03 , H03L7/085 , H03K5/1252
Abstract: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.
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公开(公告)号：US20170310310A1
公开(公告)日：2017-10-26
申请号：US15466913
申请日：2017-03-23
Applicant: Infineon Technologies AG
Inventor： Walter Kargl , Helmut Koroschetz
CPC classification number: H03K3/66 , H03K3/0372 , H03K3/0375
Abstract: According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.
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