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公开(公告)号：US09876486B2
公开(公告)日：2018-01-23
申请号：US15464600
申请日：2017-03-21
发明人： Gideon Paul
IPC分类号： H03K3/356 , H03K3/012 , H03K3/3562 , H03K3/66 , H03K5/24
CPC分类号： H03K3/012 , H03K3/356121 , H03K3/35625 , H03K3/66 , H03K5/24
摘要： Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.
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公开(公告)号：US09859877B2
公开(公告)日：2018-01-02
申请号：US15072613
申请日：2016-03-17
申请人： SK hynix Inc.
发明人： Jae Hoon Jung
摘要： A signal processing circuit may be provided. The signal processing circuit may include a mask generation circuit configured to output a mask signal in response to an internal control signal and masking information; and a masking circuit configured to mask the internal control signal in response to the mask signal, and output a masked control signal, wherein the mask generation circuit resets the mask signal in response to an internal reset signal, regardless of a pause polarity of the internal control signal.
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公开(公告)号：US20090128247A1
公开(公告)日：2009-05-21
申请号：US12064446
申请日：2006-08-23
申请人： Shigeru Kobayashi , Suguru Fujita
发明人： Shigeru Kobayashi , Suguru Fujita
CPC分类号： H04B1/7174 , H03K3/66
摘要： There is provided a small-size, low-power-consumption intermittent operation circuit capable of obtaining an output waveform having a rapid rise and fall. The intermittent operation circuit includes an active circuit (106), a first control signal generation circuit (101) for generating a first control signal (S1) for controlling the operation start and the operation end of the active circuit (106), a second control signal generation circuit (102) for generating a second control signal (S2) causing the active circuit (106) to perform ringing vibration and controlling the frequency and the amplitude value of the ringing vibration, and a timing adjusting circuit (103) for adjusting the input timing of the first and the second control signal (S1, S2) into the active circuit (106) so that the ringing vibration and the safety vibration are outputted continuously from the active circuit (106).
摘要翻译： 提供了能够获得快速上升和下降的输出波形的小尺寸，低功耗的间歇运行电路。 间歇运行电路包括有源电路（106），用于产生用于控制有源电路（106）的运行开始和运行结束的第一控制信号（S1）的第一控制信号发生电路（101） 信号发生电路（102），用于产生使有源电路（106）执行振铃振动并控制振铃的频率和振幅值的第二控制信号（S2），以及用于调整振铃振动的频率和振幅值的定时调整电路（103） 将所述第一和第二控制信号（S1，S2）的输入定时输入到所述有源电路（106）中，使得所述振铃和所述安全振动从所述有源电路（106）连续输出。
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公开(公告)号：US20080090530A1
公开(公告)日：2008-04-17
申请号：US11797610
申请日：2007-05-04
申请人： Ching-Hsing Huang
发明人： Ching-Hsing Huang
IPC分类号： H04B1/02
CPC分类号： H03B5/326 , H03K3/66 , H04L2027/0018
摘要： A transmitter IC provided with a SAW-based oscillator with an external SAW device. The transmitter IC comprises an oscillating circuit. The oscillating circuit comprises an inverter stage, a first capacitor, a second capacitor, and a resistor. The inverter stage has input and output terminals respectively coupled to two ends of the external SAW device. The first and second capacitors are respectively coupled between the input/output terminal and a ground. The resistor is coupled between the input and output terminals of the inverter stage.
摘要翻译： 一个发射器IC，配有一个带有外部SAW器件的基于SAW的振荡器。 发射机IC包括振荡电路。 振荡电路包括反相器级，第一电容器，第二电容器和电阻器。 逆变器级具有分别耦合到外部SAW器件的两端的输入和输出端子。 第一和第二电容器分别耦合在输入/输出端子和地之间。 电阻耦合在变频器级的输入和输出端子之间。
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公开(公告)号：US3857101A
公开(公告)日：1974-12-24
申请号：US36551373
申请日：1973-05-31
申请人： GEN ELECTRIC
发明人： PUCKETTE C , BUTLER W
摘要： A multi-state switch connected to DATA inputs of a counter, and NAND logic circuitry interconnected with the counter CLOCK and CLEAR inputs and CARRY output determine the number of clock pulses developed for a burst thereof occurring during the period of a lower repetition rate pulse signal applied to the counter and NAND circuit.
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公开(公告)号：US3745380A
公开(公告)日：1973-07-10
申请号：US3745380D
申请日：1971-09-16
申请人： KITAJIMA K , MITSUI M , NAGANO A , NAKAKOUJI S
发明人： MITSUI M , NAKAKOUJI S , KITAJIMA K , NAGANO A
摘要： A timing pulse generator, which produces a plurality of timing pulses, is controlled by a series connected arrangement of a monostable-multivibrator and a clock pulse generator. The monostable multivibrator or delay is triggered by an output from the timing pulse generator, so as to render the clock pulse generator disabled for a predetermined period of time, whereby both clock pulses and timing pulses will be inhibited for the predetermined period of time.
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公开(公告)号：US3566149A
公开(公告)日：1971-02-23
申请号：US3566149D
申请日：1969-06-25
申请人： LORAIN PROD CORP
摘要： A control circuit for supplying a modulated train of short duration firing pulses to each of a plurality of thyristors. A pulse suppression circuit is connected to a plurality of oscillator circuits which supply firing pulses to respective thyristors. The pulse suppression circuit disables the output of all oscillator circuits to prevent simultaneous firing of the different thyristors only during starting and only during the period preceeding the firing of each thyristor.
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公开(公告)号：US20170310310A1
公开(公告)日：2017-10-26
申请号：US15466913
申请日：2017-03-23
发明人： Walter Kargl , Helmut Koroschetz
CPC分类号： H03K3/66 , H03K3/0372 , H03K3/0375
摘要： According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.
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公开(公告)号：US09774316B2
公开(公告)日：2017-09-26
申请号：US15056144
申请日：2016-02-29
申请人： Altera Corporation
发明人： Nelson Gaspard , Yanzhong Xu
CPC分类号： H03K3/66 , G11C11/419 , H03B5/12 , H03K3/013 , H03K3/03 , H03K3/0315 , H03K5/1252 , H03L7/085
摘要： A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.
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