公开(公告)号：US20200067602A1

公开(公告)日：2020-02-27

申请号：US16669239

申请日：2019-10-30

Applicant: INPHI CORPORATION

Inventor： Mario R. HUEDA ,  José CORREA ,  Oscar E. AGAZZI

IPC: H04B10/61 ,  H04L25/03 ,  H04L7/00 ,  H04B10/079 ,  H04L1/00 ,  H04L27/26

Abstract: A method and structure for tap centering in a coherent optical receiver device. The center of gravity (CG) of the filter coefficients can be used to evaluate a proper convergence of a time-domain adaptive equalizer. However, the computation of CG in a dual-polarization optical coherent receiver is difficult when a frequency domain (FD) adaptive equalizer is adopted. In this case, the implementation of several inverse fast-Fourier transform (IFFT) stages is required to back time domain impulse response. Here, examples of the present invention estimate CG directly from the FD equalizer taps and compensate for an error of convergence based off of the estimated CG. This estimation method and associated device architecture is able to achieve an excellent tradeoff between accuracy and complexity.

公开(公告)号：US10530493B2

公开(公告)日：2020-01-07

申请号：US16212461

申请日：2018-12-06

Applicant: INPHI CORPORATION

Inventor： Mario Rafael Hueda ,  Mauro Marcelo Bruni ,  Federico Nicolas Paredes ,  Hugo Santiago Carrer ,  Diego Ernesto Crivelli ,  Oscar Ernesto Agazzi ,  Norman L. Swenson ,  Seyedmohammadreza Motaghiannezam

IPC: H04B10/61 ,  H04L7/00

Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

公开(公告)号：US10530483B2

公开(公告)日：2020-01-07

申请号：US16268702

申请日：2019-02-06

Applicant: INPHI CORPORATION

Inventor： Shih Cheng Wang ,  Jinwoo Cho ,  Shu Hao Fan

IPC: H04B10/50

Abstract: Systems and methods described herein include methods and systems for controlling bias voltage provided to an optical modulating device. The optical modulating device is biased at a bias point that is different from a null point of the device such that an offset to the received optical power due to limited extinction ratio is reduced.

公开(公告)号：US10523328B2

公开(公告)日：2019-12-31

申请号：US16249642

申请日：2019-01-16

Applicant: INPHI CORPORATION

Inventor： Karthik Gopalakrishnan ,  Jamal Riani ,  Arun Tiruvur

IPC: H04B10/40 ,  H04B10/54 ,  H04L7/00 ,  H04L7/033 ,  H03K5/00 ,  H03K19/0185 ,  H03L7/093 ,  H03L7/099 ,  H03L7/197 ,  H03L7/23 ,  H04L25/00 ,  H04L25/49

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

公开(公告)号：US10425164B2

公开(公告)日：2019-09-24

申请号：US16146936

申请日：2018-09-28

Applicant: INPHI CORPORATION

Inventor： Todd Rope ,  Radhakrishnan L. Nagarajan ,  Hari Shankar

IPC: H04B10/516 ,  G02F1/01 ,  G02F1/225 ,  H01S5/0687 ,  H01S5/40 ,  H04B10/50 ,  H01S5/14 ,  H04J14/02 ,  H04B10/556 ,  G02F1/025 ,  H01S3/067 ,  H01S5/00 ,  G02F1/21

Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. More specifically, embodiments of the present invention provide an off-quadrature modulation system. Once an off-quadrature modulation position is determined, a ratio between DC power transfer amplitude and dither tone amplitude for a modulator is as a control loop target to stabilize off-quadrature modulation. DC power transfer amplitude is obtained by measuring and sampling the output of an optical modulator. Dither tone amplitude is obtained by measuring and sampling the modulator output and performing calculation using the optical modulator output values and corresponding dither tone values. There are other embodiments as well.

公开(公告)号：US10411684B2

公开(公告)日：2019-09-10

申请号：US16153248

申请日：2018-10-05

Applicant: INPHI CORPORATION

Inventor： Irene Quek

IPC: H03K5/13 ,  H03K5/135 ,  H03M1/86 ,  H03K5/00 ,  H04L27/38

Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. In a specific embodiment, the present invention provides a phase interpolator device that mixes phase-shifted clock signals according to a predetermined weight values at predetermined time intervals. There are other embodiments as well.

公开(公告)号：US20190260477A1

公开(公告)日：2019-08-22

申请号：US16404547

申请日：2019-05-06

Applicant: INPHI CORPORATION

Inventor： Mario R. HUEDA ,  Nestor D. CAMPOS

IPC: H04B10/61

Abstract: A method and structure for equalization in coherent optical receivers. Block-based LMS (BLMS) algorithm is one of the many efficient adaptive equalization algorithms used to (i) increase convergence speed and (ii) reduce implementation complexity. Since the computation of the equalizer output and the gradient of the error are obtained using a linear convolution, BLMS can be efficiently implemented in the frequency domain with the constrained frequency-domain BLMS (FBLMS) adaptive algorithm. The present invention introduces a novel reduced complexity constrained FBLMS algorithm. This new approach replaces the two discrete Fourier transform (DFT) stages required to evaluate the DFT of the gradient error, by a simple frequency domain filtering. Implementation complexity can be drastically reduced in comparison to the standard constrained FBLMS. Furthermore, the new approach achieves better performance than that obtained with the unconstrained FBLMS in ultra-high speed coherent optical receivers.

公开(公告)号：US20190245617A1

公开(公告)日：2019-08-08

申请号：US16387209

申请日：2019-04-17

Applicant: INPHI CORPORATION

Inventor： Shih Cheng WANG ,  Seyedmohammadreza MOTAGHIANNEZAM ,  Matthew C. BASHAW

IPC: H04B10/079 ,  H04B10/2507 ,  H04L25/03 ,  H04B10/61 ,  H04L27/01 ,  H04B10/07 ,  H04L5/00

CPC classification number: H04B10/0795 ,  H04B10/07 ,  H04B10/25073 ,  H04B10/614 ,  H04B10/616 ,  H04L5/0053 ,  H04L7/0058 ,  H04L25/03 ,  H04L25/03019 ,  H04L25/03292 ,  H04L25/03878 ,  H04L27/01

Abstract: A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.

公开(公告)号：US10374750B2

公开(公告)日：2019-08-06

申请号：US16155610

申请日：2018-10-09

Applicant: INPHI CORPORATION

Inventor： Benjamin P. Smith ,  Arash Farhoodfar

IPC: H04L1/00 ,  H03M13/29 ,  H04B10/50 ,  H04B10/54 ,  H04B10/69 ,  H04B10/516 ,  H04B10/532

Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.

公开(公告)号：US20190207576A1

公开(公告)日：2019-07-04

申请号：US16294834

申请日：2019-03-06

Applicant: INPHI CORPORATION

Inventor： Simon FOREY ,  Rajasekhar NAGULAPALLI ,  Parmanand MISHRA

IPC: H03G3/22 ,  H03G7/06 ,  H03G3/30

CPC classification number: H03G1/0029 ,  H03G1/0005 ,  H03G1/0035 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/225 ,  H03G3/3078 ,  H03G7/06

Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.