公开(公告)号：US06678860B1

公开(公告)日：2004-01-13

申请号：US09633240

申请日：2000-08-07

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C2900

CPC classification number: G06F11/1024 ,  G11C2029/0411 ,  H03M13/13

Abstract: Integrated circuit memory devices include a memory cell array having therein a plurality of stored data bits and a plurality of parity bits generated from a plurality of write data bits received by the memory device during a write operation. The plurality of stored data bits and the plurality of parity bits may collectively form a word having a length of m+p bits, where m and p are integers. An error check circuit is provided that converts the plurality of stored data bits and the plurality of parity bits into a plurality of syndrome bits (e.g., Si) that designate a location of a bit error in the plurality of stored data bits when compared against the original write data bits. An error correction circuit is provided that uses the plurality of syndrome bits to correct an error in the plurality of stored data bits and generate a plurality of read data bits that match the plurality of original write data bits.

Abstract translation: 集成电路存储器件包括其中具有多个存储的数据位的存储单元阵列和在写操作期间由存储器件接收的多个写数据位产生的多个奇偶校验位。 多个存储的数据位和多个奇偶校验位可以共同形成具有m + p位长度的字，其中m和p是整数。 提供了一种错误检查电路，其将多个存储的数据位和多个奇偶校验位转换成多个校正子位（例如，Si），其指示当与多个存储的数据位相比时存储的多个存储的数据位中的位错误的位置 原始写入数据位。 提供一种纠错电路，其使用多个校正子位来校正多个存储的数据位中的错误，并生成与多个原始写入数据位匹配的多个读取数据位。

公开(公告)号：US06643201B2

公开(公告)日：2003-11-04

申请号：US10205838

申请日：2002-07-26

Applicant: Won-Seok Lee ,  Chang-Yong Lee ,  Jung-Bae Lee ,  Won-Chang Jung

Inventor： Won-Seok Lee ,  Chang-Yong Lee ,  Jung-Bae Lee ,  Won-Chang Jung

IPC: G11C700

CPC classification number: G11C7/1069 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract translation: 存储器充电电路包括根据读取控制信号和地址值控制的读取充电控制电路。 写入充电控制电路根据写入控制信号和相同或不同的地址值进行控制。 使用读取的电荷放大器电路和写入电荷放大器电路来控制对相同数据IO线的充电和充电。 列选择线路电路可以被配置成根据读控制信号和地址激活第一输出的第一布置，并且根据写控制信号和相同或不同的地址来激活第二输出。 在第二布置中，根据地址和读控制信号或写控制信号来激活第一输出。

公开(公告)号：US06477107B1

公开(公告)日：2002-11-05

申请号：US09654148

申请日：2000-09-01

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C800

CPC classification number: G11C7/1045 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  G11C8/18

Abstract: Integrated circuit memory devices include first and second memory banks, first and second local data lines electrically coupled to the first and second memory banks, respectively, and a multiplexer having first and second inputs electrically coupled to first and second data bus lines, respectively. A data selection circuit is also provided which routes data from the first and second local data lines to the first and second data bus lines, respectively, when a selection control signal is in a first logic state and routes data from the second and first local data lines to the first and second data bus lines, respectively, when a selection control signal is in a second logic state opposite the first logic state. A control signal generator is also provided. This control signal generator generates the selection control signal in the first and second logic states when a first address in a string of burst addresses is even and odd, respectively.

Abstract translation: 集成电路存储器件包括第一和第二存储体，分别电耦合到第一和第二存储体的第一和第二本地数据线以及分别具有电耦合到第一和第二数据总线的第一和第二输入的多路复用器。 还提供了一种数据选择电路，当选择控制信号处于第一逻辑状态并将来自第二和第一本地数据的数据进行路由时，分别将数据从第一和第二本地数据线路路由到第一和第二数据总线 当选择控制信号处于与第一逻辑状态相反的第二逻辑状态时，分别连接到第一和第二数据总线。 还提供控制信号发生器。 当脉冲串地址串中的第一地址分别为偶数和奇数时，该控制信号发生器产生第一和第二逻辑状态中的选择控制信号。

公开(公告)号：US06373913B1

公开(公告)日：2002-04-16

申请号：US09168535

申请日：1998-10-08

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: H03D324

CPC classification number: H03L7/0997 ,  H03K5/135 ,  H03L7/087

Abstract: An internal clock signal generator is provided which includes a synchronized delay circuit which receives an external clock signal and outputs a clock signal which is coarsely synchronized with the external clock signal. A delay locked loop (DLL) or phase locked loop (PLL) receives the coarsely synchronized clock signal and generates an internal clock signal which is more finely synchronized with the external clock signal.

Abstract translation: 提供内部时钟信号发生器，其包括同步延迟电路，其接收外部时钟信号并输出​​与外部时钟信号粗略同步的时钟信号。 延迟锁定环（DLL）或锁相环（PLL）接收粗同步的时钟信号，并产生与外部时钟信号更精细同步的内部时钟信号。

公开(公告)号：US06232797B1

公开(公告)日：2001-05-15

申请号：US09378099

申请日：1999-08-20

Applicant: Won-jae Choi ,  Jung-bae Lee ,  Si-yeol Lee

Inventor： Won-jae Choi ,  Jung-bae Lee ,  Si-yeol Lee

IPC: H03K1900

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  H03K5/135 ,  H03K19/01855

Abstract: Integrated circuit devices include a data buffer that is responsive to a control signal, enabled to pass data received at a data input thereof to a data output thereof when the control signal is in an active logic state and disabled to block passage of data from the data input to the data output when the control signal is in an inactive logic state. A data buffer control circuit is also provided. The data buffer control circuit latches a latency signal in response to a control clock, generates the control signal from the latched latency signal and comprises a pulse generator that drives the control signal to its inactive logic state in-sync with an edge of the latency signal. This inactive control signal can be used to disable the data buffer.

Abstract translation: 集成电路装置包括响应于控制信号的数据缓冲器，当控制信号处于活动逻辑状态并被禁止阻止数据从数据通过时，该数据缓冲器能够将其在其数据输入处接收的数据传送到其数据输出 当控制信号处于非活动逻辑状态时输入到数据输出。 还提供了数据缓冲器控制电路。 数据缓冲器控制电路响应于控制时钟锁存等待时间信号，从锁存的等待时间信号产生控制信号，并且包括脉冲发生器，该脉冲发生器将控制信号驱动到与等待时间信号的边沿同步的其不活动逻辑状态 。 该非活动控制信号可用于禁用数据缓冲区。

公开(公告)号：US06222411B1

公开(公告)日：2001-04-24

申请号：US09318206

申请日：1999-05-25

Applicant: Yong-gyu Chu ,  Jung-bae Lee

Inventor： Yong-gyu Chu ,  Jung-bae Lee

IPC: H03K513

CPC classification number: G11C7/225 ,  G11C7/1066 ,  G11C7/22

Abstract: Integrated circuit devices having synchronized signal generators therein include a first signal generator and a second signal generator. The first signal generator receives a first input signal and a complementary version of the first input signal at true and complementary inputs thereto, respectively, and generates a first output signal having a leading edge in-sync with a leading edge of the first input signal (e.g., clock signal CLK) but delayed relative thereto by a first time interval. The second signal generator receives the first input signal and the complementary version of the first input signal at complementary and true inputs thereto, respectively, and generates a second output signal having a leading edge in-sync with a leading edge of the complementary version of the first input signal but delayed relative thereto by the first time interval. First and second pulse generators are also preferably provided. The first pulse generator is responsive to the first output signal and the second pulse generator is responsive to the second output signal.

Abstract translation: 其中具有同步信号发生器的集成电路装置包括第一信号发生器和第二信号发生器。 第一信号发生器分别接收第一输入信号和第一输入信号的互补版本，并且产生具有与第一输入信号的前沿同步的前沿的第一输出信号（其中， 例如时钟信号CLK），但是相对于其延迟第一时间间隔。 第二信号发生器分别以互补和真实的输入分别接收第一输入信号和第一输入信号的互补版本，并产生第二输出信号，其具有与互补版本的前沿同步的前沿 第一输入信号，但相对于其延迟第一时间间隔。 也优选提供第一和第二脉冲发生器。 第一脉冲发生器响应第一输出信号，第二脉冲发生器响应第二输出信号。

公开(公告)号：US06188631B1

公开(公告)日：2001-02-13

申请号：US09498858

申请日：2000-02-07

Applicant: Jung-bae Lee ,  Woo-pyo Jeong

Inventor： Jung-bae Lee ,  Woo-pyo Jeong

IPC: G11C800

CPC classification number: G11C11/4096 ,  G11C11/4087

Abstract: A column select circuit capable of minimizing load to data input/output lines, a semiconductor memory device having the same, and an arrangement method for the semiconductor memory device are described. In the semiconductor memory device having column select circuits, each column select circuit selects one of at least two banks in a memory block and selects a predetermined bit line among a plurality of bit lines in the selected bank to transfer data of the selected bit line to data input/output line. The column select circuit includes one or more first select portions for connecting the bit lines of the selected bank to the corresponding first data lines in response to a bank select signal to select a predetermined bank. One or more second select portions connects the first data lines to a second data line in response to each column select signal which represents the address of each bit line. A third select portion connects the second data line to the data input/output lines in response to the bank select signal. The second data line shared by the second select portions is connected to at least one first data line which is responsive to the column select signal.

Abstract translation: 描述能够使对数据输入/输出线的负载最小化的列选择电路，具有该列选择电路的半导体存储器件以及用于半导体存储器件的布置方法。 在具有列选择电路的半导体存储器件中，每个列选择电路选择存储块中的至少两个存储体中的一个，并选择所选存储体中的多个位线之间的预定位线，以将所选位线的数据传送到 数据输入/输出线。 列选择电路包括一个或多个第一选择部分，用于响应于存储体选择信号选择预定存储体，将所选存储体的位线连接到对应的第一数据行。 响应于表示每个位线的地址的每个列选择信号，一个或多个第二选择部分将第一数据线连接到第二数据线。 第三选择部分响应于存储体选择信号将第二数据线连接到数据输入/输出线。 由第二选择部分共享的第二数据线被连接到响应列选择信号的至少一个第一数据线。

公开(公告)号：US6078546A

公开(公告)日：2000-06-20

申请号：US44391

申请日：1998-03-18

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1066 ,  G11C7/1072 ,  G11C7/1078

Abstract: Disclosed is a synchronous semiconductor device having a double data rate input circuit which allows data to be written in the device in response to a clock signal and a data strobe signal. The input circuit stores a pair of data which is synchronized with either the clock signal or the data strobe signal, thereby processing data at high speed. In case the data strobe is used, data setup and hold window margin is improved.

Abstract translation: 公开了具有双数据速率输入电路的同步半导体器件，其允许响应于时钟信号和数据选通信号将数据写入器件。 输入电路存储与时钟信号或数据选通信号同步的一对数据，从而高速处理数据。 在使用数据选通的情况下，数据建立和保持窗口余量得到改善。