公开(公告)号：US07872932B2

公开(公告)日：2011-01-18

申请号：US12187269

申请日：2008-08-06

Applicant: Myeong-O Kim ,  Byung-Chul Kim ,  Yong-Gyu Chu

Inventor： Myeong-O Kim ,  Byung-Chul Kim ,  Yong-Gyu Chu

IPC: G11C7/00

CPC classification number: G11C7/1048 ,  G11C7/12 ,  G11C8/18

Abstract: A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The semiconductor memory device may include a precharge unit configured to generate a plurality of precharge signals and a controller configured to control precharging of the at least one local input/output line responsive to block information corresponding to activation of at least one of the memory cell array blocks and responsive to at least one of the precharge signals.

Abstract translation: 一种用于对本地输入/输出线进行预充电的方法和半导体存储器件。 可以具有开放位线结构的半导体存储器件通过耦合到第一至第n存储器单元阵列块（n为自然数）的位线的本地输入/输出线传输数据。 半导体存储器件可以包括：预充电单元，其被配置为产生多个预充电信号;以及控制器，被配置为响应于对应于至少一个存储单元阵列的激活来控制至少一个本地输入/输出线的预充电 并且响应于至少一个预充电信号。

公开(公告)号：US20060098506A1

公开(公告)日：2006-05-11

申请号：US11267203

申请日：2005-11-04

Applicant: Gyu-Yeol Kim ,  Sang-Man Byun ,  Yong-Gyu Chu ,  Seok-Ho Park

Inventor： Gyu-Yeol Kim ,  Sang-Man Byun ,  Yong-Gyu Chu ,  Seok-Ho Park

IPC: G11C29/00

CPC classification number: G11C29/48 ,  G11C29/10 ,  G11C29/1201

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Abstract translation: 提供可以写入不同数据位的信息的半导体存储器件，以及电半导体存储器件的电测试方法。 在用于测试半导体存储器件的存储单元阵列的模式中，半导体存储器包括一个控制信号生成焊盘，当数据被写入存储单元阵列时，该控制信号产生焊盘能够将不相同的数据写入每个组的数据输入/输出焊盘。

公开(公告)号：US06678206B2

公开(公告)日：2004-01-13

申请号：US10106931

申请日：2002-03-25

Applicant: Yong-Gyu Chu ,  Kyu-Chan Lee

Inventor： Yong-Gyu Chu ,  Kyu-Chan Lee

IPC: G11C800

CPC classification number: G11C8/18 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2227 ,  H03L7/0812 ,  H03L7/089 ,  H03L7/0891

Abstract: A semiconductor memory device including a delay locked loop (DLL) that is capable of turning off the DLL in a precharge mode while maintaining locking information stored before the DLL operates in the precharge mode is provided. The DLL includes an ON/OFF mode for turning the DLL on or off. The DLL also includes a standby mode for turning the DLL off while still maintaining locking information stored before the DLL operates in a precharge mode in response to the activation of a standby enabling signal. The standby enabling signal is inactive when the DLL locks. The standby enabling signal is active when DLL lock is complete.

Abstract translation: 提供一种包括延迟锁定环（DLL）的半导体存储器件，其能够在保持DLL在预充电模式之前存储的锁定信息的同时以预充电模式关闭DLL。 该DLL包括用于打开或关闭DLL的ON / OFF模式。 DLL还包括用于响应于待机使能信号的激活而在DLL在预充电模式之前存储的锁定信息的同时仍然保持关闭DLL的待机模式。 当DLL锁定时，待机启用信号无效。 当DLL锁定完成时，待机启用信号有效。

公开(公告)号：US20130315004A1

公开(公告)日：2013-11-28

申请号：US13833740

申请日：2013-03-15

Applicant: Yong Gyu Chu ,  Hyo Soon Kang ,  Seung Bum KO ,  Sang Jae Rhee

Inventor： Yong Gyu Chu ,  Hyo Soon Kang ,  Seung Bum KO ,  Sang Jae Rhee

IPC: G11C7/10 ,  H01L23/48 ,  H01L21/50

CPC classification number: G11C7/10 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/22 ,  G11C2207/105 ,  H01L21/50 ,  H01L23/48 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2924/1434

Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract translation: 半导体器件包括存储单元阵列，焊盘组，第一可选焊盘，第二可选焊盘和数据输入多路复用器块，其被配置为基于是否通过全部或部分焊盘组输入数据到存储器单元阵列 所述第一可选焊盘和接地彼此连接，其中所述数据输入多路复用器块被配置为基于所述焊盘组中的所述第二焊盘组或所述焊盘组中的第二焊盘组作为所述焊盘组的一部分来选择所述焊盘组中的第一焊盘组， 选项板和地面相互连接。

公开(公告)号：US20080170451A1

公开(公告)日：2008-07-17

申请号：US11971606

申请日：2008-01-09

Applicant: Yong-gyu Chu

Inventor： Yong-gyu Chu

IPC: G11C29/00

CPC classification number: G11C29/46

Abstract: A test mode setting method and circuit that reduce the number of signal lines, thereby minimizing the number of wires of a semiconductor memory device. The method includes: sequentially activating a plurality of selection signals; when each selection signal is activated, activating one of a plurality of test mode addresses corresponding to the activated selection signal; when the last one of the selection signals is activated, and one of the test mode addresses corresponding to the last selection signal is activated, activating a test mode corresponding to the activated test mode address.

Abstract translation: 一种减少信号线数目的测试模式设置方法和电路，从而最小化半导体存储器件的导线数量。 该方法包括：顺序激活多个选择信号; 当每个选择信号被激活时，激活对应于所激活的选择信号的多个测试模式地址中的一个; 当最后一个选择信号被激活时，与最后一个选择信号对应的一个测试模式地址被激活，激活对应于激活的测试模式地址的测试模式。

公开(公告)号：US06909650B2

公开(公告)日：2005-06-21

申请号：US10716773

申请日：2003-11-19

Applicant: Jin-ho Ryu ,  Choong-sun Shin ,  Yong-gyu Chu

Inventor： Jin-ho Ryu ,  Choong-sun Shin ,  Yong-gyu Chu

IPC: G11C29/00 ,  G11C29/48 ,  G11C7/00

CPC classification number: G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

Abstract: Provided are a circuit and a method for transforming a data input/output format of a semiconductor memory device which is capable of generating various types of data patterns when the number of memory cells connected to one column selection line is greater than the number of data input pins. The circuit for transforming a data input/output format of a semiconductor memory device includes a first transmission circuit, a second transmission circuit, and a mode register set (MRS). The first transmission circuit is activated when a first test mode signal is enabled, receives n data inputs from n data input ends, and transmits the n data inputs to m memory cells. Here, n and m are natural numbers and m is greater than n. The second transmission circuit is activated when a second test mode signal is enabled, receives n data inputs from the n data input ends, and transmits the n data inputs to the m memory cells. The mode register set (MRS) receives a command and an address from outside the semiconductor device and outputs the first test mode signal and the second test mode signal according to combinations of the command and the address. In particular, data that is transmitted to adjacent memory cells of the m memory cells is inputted to different input ends of the n data input ends.

Abstract translation: 提供一种用于变换半导体存储器件的数据输入/输出格式的电路和方法，当连接到一列选择线的存储单元的数量大于数据输入的数量时，能够产生各种类型的数据模式 针脚。 用于变换半导体存储器件的数据输入/输出格式的电路包括第一传输电路，第二传输电路和模式寄存器集（MRS）。 当启用第一测试模式信号时，第一传输电路被激活，从n个数据输入端接收n个数据输入，并将n个数据输入发送到m个存储单元。 这里，n和m是自然数，m大于n。 当启用第二测试模式信号时，第二传输电路被激活，从n个数据输入端接收n个数据输入，并将n个数据输入发送到m个存储单元。 模式寄存器组（MRS）从半导体器件外部接收命令和地址，并根据命令和地址的组合输出第一测试模式信号和第二测试模式信号。 特别地，发送到m个存储单元的相邻存储单元的数据被输入到n个数据输入端的不同的输入端。

公开(公告)号：US06222411B1

公开(公告)日：2001-04-24

申请号：US09318206

申请日：1999-05-25

Applicant: Yong-gyu Chu ,  Jung-bae Lee

Inventor： Yong-gyu Chu ,  Jung-bae Lee

IPC: H03K513

CPC classification number: G11C7/225 ,  G11C7/1066 ,  G11C7/22

Abstract: Integrated circuit devices having synchronized signal generators therein include a first signal generator and a second signal generator. The first signal generator receives a first input signal and a complementary version of the first input signal at true and complementary inputs thereto, respectively, and generates a first output signal having a leading edge in-sync with a leading edge of the first input signal (e.g., clock signal CLK) but delayed relative thereto by a first time interval. The second signal generator receives the first input signal and the complementary version of the first input signal at complementary and true inputs thereto, respectively, and generates a second output signal having a leading edge in-sync with a leading edge of the complementary version of the first input signal but delayed relative thereto by the first time interval. First and second pulse generators are also preferably provided. The first pulse generator is responsive to the first output signal and the second pulse generator is responsive to the second output signal.

Abstract translation: 其中具有同步信号发生器的集成电路装置包括第一信号发生器和第二信号发生器。 第一信号发生器分别接收第一输入信号和第一输入信号的互补版本，并且产生具有与第一输入信号的前沿同步的前沿的第一输出信号（其中， 例如时钟信号CLK），但是相对于其延迟第一时间间隔。 第二信号发生器分别以互补和真实的输入分别接收第一输入信号和第一输入信号的互补版本，并产生第二输出信号，其具有与互补版本的前沿同步的前沿 第一输入信号，但相对于其延迟第一时间间隔。 也优选提供第一和第二脉冲发生器。 第一脉冲发生器响应第一输出信号，第二脉冲发生器响应第二输出信号。

公开(公告)号：US08315118B2

公开(公告)日：2012-11-20

申请号：US12767830

申请日：2010-04-27

Applicant: Yong-Gyu Chu ,  Woo-Pyo Jeong

Inventor： Yong-Gyu Chu ,  Woo-Pyo Jeong

IPC: G11C7/00

CPC classification number: G11C8/12 ,  G11C7/12 ,  G11C11/4094

Abstract: A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times.

Abstract translation: 提供了一种半导体存储器件的预充电方法，其在银行预充电操作期间控制每个存储体的预充电开始时间，以及使用该方法的半导体存储器件。 该装置可以锁存相应组的有效或写入顺序，并且在多组预充电操作期间根据锁存的有效或写入顺序不同地控制各个存储体的预充电开始时间，以允许多个存储体在不同时间开始预充电操作 。

公开(公告)号：US20080316846A1

公开(公告)日：2008-12-25

申请号：US12201996

申请日：2008-08-29

Applicant: Gyu-Yeol KIM ,  Sang-Man BYUN ,  Yong-Gyu CHU ,  Seok-Ho PARK

Inventor： Gyu-Yeol KIM ,  Sang-Man BYUN ,  Yong-Gyu CHU ,  Seok-Ho PARK

IPC: G11C29/00 ,  G11C8/00

CPC classification number: G11C29/48 ,  G11C29/10 ,  G11C29/1201

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Abstract translation: 提供可以写入不同数据位的信息的半导体存储器件，以及电半导体存储器件的电测试方法。 在用于测试半导体存储器件的存储单元阵列的模式中，半导体存储器包括一个控制信号生成焊盘，当数据被写入存储单元阵列时，该控制信号产生焊盘能够将不相同的数据写入每个组的数据输入/输出焊盘。

公开(公告)号：US07420871B2

公开(公告)日：2008-09-02

申请号：US11609865

申请日：2006-12-12

Applicant: Yong-Gyu Chu

Inventor： Yong-Gyu Chu

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

Abstract: Provided is a synchronous semiconductor memory device with improved latency control. In one embodiment, the synchronous semiconductor memory device may include a clock synchronizing circuit, a latency circuit, and a latency control circuit. The clock synchronizing circuit may receive an external clock signal and output a data output clock signal. The latency circuit may store a read signal in response to at least one sampling clock signal, generate a plurality of clock control signals in a sequential manner, generate a plurality of transfer clock signals synchronized with the plurality of clock control signals, and supply a latency signal in response to the transfer clock signals. The latency control circuit may delay the plurality of clock control signals by the sum of output delay time and the read command delay time so as to generate a plurality of sampling clock signals synchronized with the plurality of delayed clock control signals.

Abstract translation: 提供了具有改进的等待时间控制的同步半导体存储器件。 在一个实施例中，同步半导体存储器件可以包括时钟同步电路，等待时间电路和等待时间控制电路。 时钟同步电路可以接收外部时钟信号并输出​​数据输出时钟信号。 延迟电路可以响应于至少一个采样时钟信号存储读取信号，以顺序方式产生多个时钟控制信号，产生与多个时钟控制信号同步的多个传输时钟信号，并提供等待时间 响应于传输时钟信号的信号。 等待时间控制电路可以通过输出延迟时间和读命令延迟时间的和来延迟多个时钟控制信号，以便产生与多个延迟的时钟控制信号同步的多个采样时钟信号。