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公开(公告)号：US11552646B2
公开(公告)日：2023-01-10
申请号：US17354126
申请日：2021-06-22
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Vikram Singh
Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.
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公开(公告)号：US11550749B2
公开(公告)日：2023-01-10
申请号：US17143679
申请日：2021-01-07
Inventor： Manoj Kumar , Kailash Kumar , Nicolas Demange
Abstract: A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.
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公开(公告)号：US11550531B2
公开(公告)日：2023-01-10
申请号：US17380754
申请日：2021-07-20
Inventor： Benedetto Vigna , Mahesh Chowdhary , Matteo Dameno
Abstract: A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.
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公开(公告)号：US11532633B2
公开(公告)日：2022-12-20
申请号：US17491201
申请日：2021-09-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tushar Sharma , Tanmoy Roy , Shishir Kumar
IPC: G11C11/00 , H01L27/11 , G11C5/06 , G11C11/412 , H01L27/02 , G11C8/16 , G11C11/417
Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
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公开(公告)号：US11531873B2
公开(公告)日：2022-12-20
申请号：US16909673
申请日：2020-06-23
Inventor： Thomas Boesch , Giuseppe Desoli , Surinder Pal Singh , Carmine Cappetta
Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.
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Patent Agency Ranking
公开(公告)号：US11520721B2
公开(公告)日：2022-12-06
申请号：US16933752
申请日：2020-07-20
Inventor： Nirav Prashantkumar Trivedi , Sandip Atal , Rolf Nandlinger
Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.
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公开(公告)号：US11513883B2
公开(公告)日：2022-11-29
申请号：US17161832
申请日：2021-01-29
Applicant: STMicroelectronics International N.V.
Inventor： Charul Jain , Asif Rashid Zargar
IPC: G06F11/07
Abstract: An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.
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公开(公告)号：US11513544B1
公开(公告)日：2022-11-29
申请号：US17537010
申请日：2021-11-29
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Mayankkumar Hareshbhai Niranjani , Dhulipalla Phaneendra Kumar , Gourav Garg , Sourabh Banzal
Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
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公开(公告)号：US11507831B2
公开(公告)日：2022-11-22
申请号：US16799671
申请日：2020-02-24
Inventor： Surinder Pal Singh , Thomas Boesch , Giuseppe Desoli
Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.
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公开(公告)号：US11502659B2
公开(公告)日：2022-11-15
申请号：US16903552
申请日：2020-06-17
Applicant: STMicroelectronics International N.V.
Inventor： Riju Biswas
IPC: H03G3/30 , G01S13/931 , H03F3/45
Abstract: Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.
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