Methods of forming trench/via features in an underlying structure using a process that includes a masking layer formed by a directed self-assembly process
    191.
    发明授权
    Methods of forming trench/via features in an underlying structure using a process that includes a masking layer formed by a directed self-assembly process 有权
    在下层结构中使用包括通过定向自组装工艺形成的掩模层的工艺形成沟槽/通孔特征的方法

    公开(公告)号:US08906802B2

    公开(公告)日:2014-12-09

    申请号:US13839284

    申请日:2013-03-15

    CPC classification number: H01L21/31144 H01L21/0337 H01L21/76816

    Abstract: One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material.

    Abstract translation: 本文公开的一种说明性方法包括以下步骤:执行定向自组装过程以形成DSA掩模层,执行至少一个处理操作以去除DSA掩模层的至少一个特征,从而限定图案化DSA 具有DSA掩模图案的掩模层,执行至少一个处理操作以形成图案化的传输掩蔽层,其具有由在传送掩蔽层中限定多个开口的多个特征组成的传输掩蔽图案,其中传输掩蔽图案是 DSA掩模图案的反向,并且通过在材料层上的图案化转印掩模层进行至少一个蚀刻工艺以在材料层中形成多个沟槽/通孔特征。

    METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE USING A PROCESS THAT INCLUDES A MASKING LAYER FORMED BY A DIRECTED SELF-ASSEMBLY PROCESS
    192.
    发明申请
    METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE USING A PROCESS THAT INCLUDES A MASKING LAYER FORMED BY A DIRECTED SELF-ASSEMBLY PROCESS 有权
    使用包含由指导的自组装过程形成的掩蔽层的过程在基础结构中形成TRENCH /通过特征的方法

    公开(公告)号:US20140273469A1

    公开(公告)日:2014-09-18

    申请号:US13839284

    申请日:2013-03-15

    CPC classification number: H01L21/31144 H01L21/0337 H01L21/76816

    Abstract: One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material.

    Abstract translation: 本文公开的一种说明性方法包括以下步骤:执行定向自组装过程以形成DSA掩模层,执行至少一个处理操作以去除DSA掩模层的至少一个特征,从而限定图案化DSA 具有DSA掩模图案的掩模层,执行至少一个处理操作以形成图案化的传输掩蔽层,其具有由在传送掩蔽层中限定多个开口的多个特征组成的传输掩蔽图案,其中传输掩蔽图案是 DSA掩模图案的反向,并且通过在材料层上的图案化转印掩模层进行至少一个蚀刻工艺以在材料层中形成多个沟槽/通孔特征。

    INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING METAL GATE ELECTRODES
    193.
    发明申请
    INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING METAL GATE ELECTRODES 有权
    用于制作金属门电极的集成电路的集成电路和方法

    公开(公告)号:US20140231885A1

    公开(公告)日:2014-08-21

    申请号:US13773397

    申请日:2013-02-21

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中,用于制造集成电路的方法包括在半导体衬底上提供牺牲栅极结构。 牺牲栅极结构在两个间隔物之间​​包括两个间隔物和牺牲栅极材料。 该方法将牺牲栅极材料的一部分凹入两个间隔物之间​​。 在使用牺牲栅极材料作为掩模的同时蚀刻两个间隔物的上部区域。 该方法包括去除牺牲栅极材料的剩余部分并暴露两个间隔物的下部区域。 第一金属沉积在两个间隔物的下部区域之间。 第二金属沉积在两个间隔物的上部区域之间。

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