公开(公告)号：US09508562B2

公开(公告)日：2016-11-29

申请号：US14316988

申请日：2014-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ji Xu ,  Richard A. Farrell ,  Gerard M. Schmid ,  Moshe E Preil

IPC: H01L21/3213 ,  H01L21/308 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/28 ,  G03F7/00 ,  H01L21/311 ,  C08L53/00 ,  G03F1/00

CPC classification number: H01L21/32139 ,  B81C2201/0198 ,  C08L53/00 ,  C08L53/005 ,  G03F1/00 ,  G03F7/0002 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816

Abstract: In one example, a method includes forming a template having a plurality of elements above a process layer and forming spacers on sidewalls of the plurality of elements. Portions of the process layer are exposed between adjacent spacers. At least one of the plurality of elements is removed. A mask structure is formed from a directed self-assembly material over the exposed portions. The process layer is patterned using at least the mask structure as an etch mask.

Abstract translation: 在一个示例中，一种方法包括在工艺层上形成具有多个元件的模板，并在多个元件的侧壁上形成间隔物。 处理层的一部分暴露在相邻间隔物之间​​。 去除多个元件中的至少一个。 掩模结构由暴露部分上的定向自组装材料形成。 使用至少掩模结构作为蚀刻掩模对工艺层进行图案化。

公开(公告)号：US09275896B2

公开(公告)日：2016-03-01

申请号：US14341985

申请日：2014-07-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Deniz Elizabeth Civay ,  Ji Xu ,  Gerard Schmid ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76802 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用覆盖在半导体衬底上的蚀刻层的侧壁来形成引导限制阱的图形外延生成DSA。 使用嵌段共聚物填充指向封闭的石墨电极DSA。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 蚀刻相位被蚀刻，同时使耐腐蚀相位基本上到位以限定具有纳米图案的蚀刻掩模。 将纳米图案转移到蚀刻层。

公开(公告)号：US20150380252A1

公开(公告)日：2015-12-31

申请号：US14316988

申请日：2014-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ji Xu ,  Richard A. Farrell ,  Gerard M. Schmid ,  Moshe E. Preil

IPC: H01L21/28 ,  H01L21/3213

CPC classification number: H01L21/32139 ,  B81C2201/0198 ,  C08L53/00 ,  C08L53/005 ,  G03F1/00 ,  G03F7/0002 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816

Abstract: In one example, a method includes forming a template having a plurality of elements above a process layer and forming spacers on sidewalls of the plurality of elements. Portions of the process layer are exposed between adjacent spacers. At least one of the plurality of elements is removed. A mask structure is formed from a directed self-assembly material over the exposed portions. The process layer is patterned using at least the mask structure as an etch mask.

Abstract translation: 在一个示例中，一种方法包括在工艺层上形成具有多个元件的模板，并在多个元件的侧壁上形成间隔物。 处理层的一部分暴露在相邻间隔物之间​​。 去除多个元件中的至少一个。 掩模结构由暴露部分上的定向自组装材料形成。 使用至少掩模结构作为蚀刻掩模对工艺层进行图案化。

公开(公告)号：US09530689B2

公开(公告)日：2016-12-27

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针脚。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US20160035565A1

公开(公告)日：2016-02-04

申请号：US14692359

申请日：2015-04-21

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ji Xu ,  Gerard Schmid ,  Richard A. Farrell

IPC: H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/0274

Abstract: Methods for directed self-assembly (DSA) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an A or B-block attracting layer over a base semiconductor layer, forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or SAMs layer coating within the trench and over the base semiconductor layer. The method further includes forming a block copolymer layer over the neutral layer coating and over the A or B-block attracting layer and annealing the block copolymer layer to form a plurality of vertically-oriented, cylindrical structures within the block copolymer layer.

Abstract translation: 本文公开了在集成电路的设计和制造中使用化学外延的定向自组装（DSA）的方法。 一种示例性方法包括在基底半导体层上形成A或B块吸引层，在A或B块吸引层中形成沟槽以暴露基底半导体层的一部分，以及形成中性刷或垫或SAM 在该沟槽内和该基底半导体层上方涂层。 该方法还包括在中性层涂层上和在A或B嵌段吸引层之上形成嵌段共聚物层，并使嵌段共聚物层退火以在嵌段共聚物层内形成多个垂直取向的圆柱形结构。

公开(公告)号：US20150303055A1

公开(公告)日：2015-10-22

申请号：US14254460

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ji Xu ,  Gerard Schmid ,  Richard A. Farrell

IPC: H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0276 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes surface treating exposed portions of an anti-reflective coating (ARC) that overlie a semiconductor substrate to form surface treated ARC portions. A neutral layer is formed overlying the anti-reflective coating including over the surface treated ARC portions. First portions of the neutral layer are selectively removed and second portions of the anti-reflective coating that are disposed under the first portions laterally adjacent to the surface treated ARC portions are exposed to define a guide pattern. A block copolymer layer is deposited overlying the guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the guide pattern.

Abstract translation: 提供了制造集成电路的方法。 在一个实例中，用于制造集成电路的方法包括：表面处理覆盖在半导体衬底上以形成经表面处理的ARC部分的抗反射涂层（ARC）的暴露部分。 形成覆盖在抗反射涂层上的中性层，包括在经表面处理的ARC部分上。 中性层的第一部分被选择性地去除，并且设置在与表面处理的ARC部分横向相邻的第一部分下面的抗反射涂层的第二部分被暴露以限定引导图案。 沉积在引导图案上的嵌段共聚物层。 嵌段共聚物层被相分离以限定与导向图案对应的纳米图案。

公开(公告)号：US09478506B2

公开(公告)日：2016-10-25

申请号：US13787090

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard A. Farrell ,  Gerard M. Schmid ,  Sudharshanan Raghunathan

IPC: H01L21/311 ,  H01L23/00 ,  H01L21/308 ,  H01L21/683 ,  H01L21/768 ,  H01L21/67

CPC classification number: H01L23/564 ,  H01L21/3086 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers.

Abstract translation: 提供了用于化学导轨的多层图案转印的方法。 在典型的实施例中，通过在衬底（例如，硅（Si））上形成蚀刻掩模层（例如，氮化物层和氧化物层）来形成器件。 然后在蚀刻掩模层上形成取向控制层（例如中性层），并且在取向控制层上形成ARC层（例如SiARC）。 在其它实施例中，也可以在ARC层和取向控制层之间形成有机平坦化层（OPL）和/或保护层。 无论如何，可以通过ARC和/或其他层形成锥形蚀刻轮廓/图案。

公开(公告)号：US20160300754A1

公开(公告)日：2016-10-13

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针迹。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US20140377965A1

公开(公告)日：2014-12-25

申请号：US13921520

申请日：2013-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerard M. Schmid ,  Ji Xu ,  Richard A. Farrell

IPC: H01L21/02

CPC classification number: G03F7/0002 ,  H01L21/0271

Abstract: An illustrative DSA formulation disclosed herein includes a block copolymer material, a casting solvent and at least one plasticizer agent. An illustrative method disclosed herein includes depositing a liquid DSA formulation on a guide layer, performing a spin-coating process to form a DSA-based material layer comprised of the liquid DSA formulation above the guide layer, wherein the DSA-based material layer includes at least one plasticizing agent and, after performing the spin-coating process, performing at least one heating process on the DSA-based material layer while at least some of the plasticizing agent remains in the DSA-based material layer so as to enable phase separation of block copolymer materials.

Abstract translation: 本文公开的说明性DSA制剂包括嵌段共聚物材料，浇铸溶剂和至少一种增塑剂。 本文公开的说明性方法包括在引导层上沉积液体DSA制剂，进行旋涂工艺以形成由引导层上方的液体DSA制剂构成的基于DSA的材料层，其中基于DSA的材料层包括在 至少一种增塑剂，并且在进行旋涂工艺之后，在基于DSA的材料层上进行至少一个加热过程，而至少一些增塑剂保留在基于DSA的材料层中，以使得能够相位分离 嵌段共聚物材料。

公开(公告)号：US08889343B2

公开(公告)日：2014-11-18

申请号：US13726732

申请日：2012-12-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Moshe E Preil ,  Gerard M. Schmid ,  Richard A. Farrell ,  Ji Xu ,  Thomas I. Wallow

IPC: G03F7/26 ,  G03F7/20

CPC classification number: G03F7/0002

Abstract: Approaches for utilizing laser annealing to optimize lithographic processes such as directed self assembly (DSA) are provided. Under a typical approach, a substrate (e.g., a wafer) will be subjected to a lithographic process (e.g., having a set of stages/phases, aspects, etc.) such as DSA. Before or during such process, a set of laser annealing passes/scans will be made over the substrate to optimize one or more of the stages. In addition, the substrate could be subjected to additional processes such as hotplate annealing, etc. Still yet, in making a series of laser annealing passes, the techniques utilized and/or beam characteristics of each pass could be varied to further optimize the results.

Abstract translation: 提供了利用激光退火优化光刻工艺的方法，如定向自组装（DSA）。 在典型的方法下，衬底（例如，晶片）将经历诸如DSA的光刻工艺（例如，具有一组阶段/阶段，方面等）。 在此过程之前或期间，将在衬底上进行一组激光退火通过/扫描以优化一个或多个阶段。 此外，可以对基板进行额外的加工，例如热板退火等。然而，在进行一系列激光退火过程中，可以改变所使用的技术和/或每个通过的光束特性以进一步优化结果。