公开(公告)号：US20170263777A1

公开(公告)日：2017-09-14

申请号：US15609513

申请日：2017-05-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02 ,  H01L27/02 ,  H01L27/108 ,  H01L27/12 ,  H01L21/84 ,  H01L25/16

CPC classification number: H01L29/7869 ,  H01L21/84 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L25/16 ,  H01L27/0222 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/20 ,  H01L28/60 ,  H01L29/78609 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

公开(公告)号：US20170256756A1

公开(公告)日：2017-09-07

申请号：US15596161

申请日：2017-05-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroyuki MIYAKE

IPC: H01M2/02

CPC classification number: H01M2/0237 ,  H01M2/021 ,  H01M2/0212 ,  H01M2/0275 ,  H01M2220/20 ,  H01M2220/30

Abstract: Provided is a secondary battery suitable for a portable information terminal or a wearable device, or an electronic device having a novel structure with a variety of forms and a secondary battery that fits the form of the electronic device. The secondary battery is sealed using a film having projections that can reduce stress on the film caused when external force is applied. The film has a pattern of projections formed by pressing (e.g., embossing). A top portion of each of the projections has a region thicker than a bottom portion of each of the projections. The thickness of the top portion of each of the projections is 1.5 or more times, preferably 2 or more times, as large as that of the bottom portion of each of the projections, and is a thickness such that each of the projections has a convex space.

公开(公告)号：US20170200413A1

公开(公告)日：2017-07-13

申请号：US15410094

申请日：2017-01-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki MIYAKE ,  Shunpei YAMAZAKI

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/0233 ,  G09G2320/045

Abstract: A light-emitting device in which variation in luminance among pixels is suppressed. The light-emitting device includes a pixel; a first circuit configured to generate a signal containing information on a value of current extracted from the pixel;and a second circuit configured to correct an image signal in accordance with the signal. The pixel includes a light-emitting element; a transistor for controlling supply of the current to the light-emitting element in accordance with the image signal; a first switch configured to control connection between a gate and a drain of the transistor or between the gate of the transistor and a wiring; and a second switch configured to control extraction of the current from the pixel.

公开(公告)号：US20170179161A1

公开(公告)日：2017-06-22

申请号：US15391938

申请日：2016-12-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi UMEZAKI ,  Hiroyuki MIYAKE

IPC: H01L27/12 ,  G09G3/20 ,  H01L27/02

CPC classification number: H01L27/124 ,  G09G3/2092 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/061 ,  G09G2320/0646 ,  G09G2320/0666 ,  G11C19/28 ,  H01L27/0207 ,  H01L27/1222 ,  H01L27/1225

Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor, a clock signal is input to a gate electrode of the first switching transistor, and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

公开(公告)号：US20170148408A1

公开(公告)日：2017-05-25

申请号：US15393389

申请日：2016-12-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiko AMANO ,  Hiroyuki MIYAKE

IPC: G09G3/36 ,  G11C19/28 ,  G06F1/32 ,  H01L27/12

Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

公开(公告)号：US20170053948A1

公开(公告)日：2017-02-23

申请号：US15341069

申请日：2016-11-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki MIYAKE

IPC: H01L27/12 ,  H01L33/62

CPC classification number: H01L27/1225 ,  G09G3/3233 ,  G09G3/3275 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/045 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3241 ,  H01L33/62

Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.

Abstract translation: 目的是为了防止操作缺陷，并且减小场效应晶体管的阈值电压的波动的影响。 提供场效应晶体管，开关和电容器。 场效应晶体管包括第一栅极和第二栅极，第一栅极和第二栅极之间具有沟道形成区域彼此重叠，并且场效应晶体管的阈值电压根据第二栅极的电位而变化。 该开关具有确定场效应晶体管的源极和漏极之一与场效应晶体管的第二栅极之间的电连接是否建立的功能。 电容器具有在场效应晶体管的第二栅极和场效应晶体管的源极和漏极之间保持电压的功能。

公开(公告)号：US20170033110A1

公开(公告)日：2017-02-02

申请号：US15292362

申请日：2016-10-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

Abstract translation: 本发明的目的是提供一种能够抑制功耗的存储器件和包括存储器件的半导体器件。 作为用作保持蓄积在用作存储元件的晶体管中的电荷的开关元件，为存储器件中的每个存储单元提供包括作为有源层的氧化物半导体膜的晶体管。 用作存储元件的晶体管具有第一栅电极，第二栅电极，位于第一栅电极和第二栅电极之间的半导体膜，位于第一栅电极和半导体膜之间的第一绝缘膜， 位于第二栅电极和半导体膜之间的第二绝缘膜，以及与半导体膜接触的源电极和漏电极。

公开(公告)号：US20170012453A1

公开(公告)日：2017-01-12

申请号：US15274323

申请日：2016-09-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Junpei MOMO ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI

IPC: H02J7/00 ,  H01M10/0525 ,  H01M10/42 ,  H01M10/46 ,  H01M10/44

Abstract: A decrease in the capacity of a power storage device is inhibited by adjusting or reducing imbalance in the amount of inserted and extracted carrier ions between positive and negative electrodes, which is caused by decomposition of an electrolyte solution of the negative electrode. Further, the capacity of the power storage device can be restored. Furthermore, impurities in the electrolyte solution can be decomposed with the use of the third electrode. A power storage device including positive and negative electrodes, an electrolyte, and a third electrode is provided. The third electrode has an adequate electrostatic capacitance. The third electrode can include a material with a large surface area. In addition, a method for charging the power storage device including the steps of performing charging by applying a current between the positive and negative electrodes, and performing additional applying a current between the third electrode and the negative electrode is provided.

Abstract translation: 通过调节或减少由负极的电解液的分解引起的正极和负极之间的插入和提取的载流子的量的不平衡，可以抑制蓄电装置的容量的减小。 此外，可以恢复蓄电装置的容量。 此外，电解质溶液中的杂质可以通过使用第三电极而分解。 提供了包括正极和负极，电解质和第三电极的蓄电装置。 第三电极具有足够的静电电容。 第三电极可以包括具有大表面积的材料。 另外，提供了一种蓄电装置的充电方法，包括以下步骤：通过在正极和负极之间施加电流并且在第三电极和负极之间执行附加的电流来进行充电。

公开(公告)号：US20160365359A1

公开(公告)日：2016-12-15

申请号：US15239006

申请日：2016-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kouhei TOYOTAKA ,  Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: H01L27/12 ,  G09G3/3233 ,  G09G3/3258 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/1362 ,  H01L29/786 ,  G09G3/36

CPC classification number: H01L27/124 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0626 ,  G09G2330/021 ,  G11C19/28 ,  G11C19/287 ,  H01L27/1225 ,  H01L29/7869

Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

公开(公告)号：US20160328080A1

公开(公告)日：2016-11-10

申请号：US15140825

申请日：2016-04-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki MIYAKE

IPC: G06F3/041 ,  G02F1/1362 ,  G09G3/36

Abstract: Provided is a novel touch panel that is highly convenience or reliable, a novel data processor that is highly convenient or reliable, a novel touch panel, a novel data processor, or a novel semiconductor device. The touch panel includes a sensor element and a display element. The sensor element includes a first conductive film and a second conductive film. The display element includes a layer containing a liquid crystal material and a third conductive film which is provided so that an electric field controlling the alignment of the liquid crystal material contained in the layer can be applied between the first conductive film and the third conductive film.

Abstract translation: 提供了一种高度便利或可靠的新型触摸面板，一种非常方便或可靠的新型数据处理器，新颖的触摸面板，新颖的数据处理器或新颖的半导体器件。 触摸面板包括传感器元件和显示元件。 传感器元件包括第一导电膜和第二导电膜。 显示元件包括含有液晶材料的层和第三导电膜，该第三导电膜被设置为使得可以在第一导电膜和第三导电膜之间施加控制该层中包含的液晶材料的取向的电场。