公开(公告)号：US11171053B2

公开(公告)日：2021-11-09

申请号：US16422559

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Lin-Yu Huang ,  Huan-Chieh Su ,  Sheng-Tsung Wang ,  Zhi-Chang Lin ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

公开(公告)号：US20210313464A1

公开(公告)日：2021-10-07

申请号：US17353089

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

公开(公告)号：US20210273062A1

公开(公告)日：2021-09-02

申请号：US16881481

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8234

Abstract: A method includes providing a structure having a substrate, a gate, a gate spacer, a dielectric gate cap, a source/drain (S/D) feature, a contact etch stop layer (CESL) covering a sidewall of the gate spacer and a top surface of the S/D feature, and an inter-level dielectric (ILD) layer. The method includes etching a contact hole through the ILD layer and through a portion of the CESL, the contact hole exposing the CESL covering the sidewalls of the gate spacer and exposing a top portion of the S/D feature. The method includes forming a silicide feature on the S/D feature and selectively depositing an inhibitor on the silicide feature. The inhibitor is not deposited on surfaces of the CESL other than at a corner area where the CESL and the silicide feature meet.

公开(公告)号：US20210074819A1

公开(公告)日：2021-03-11

申请号：US17099304

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Tsung Wang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/40 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/45

Abstract: A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, a dielectric feature disposed In the ILD layer and contacting the second epitaxial S/D feature, and a conductive feature disposed in the ILD layer and contacting the first epitaxial S/D feature, where a portion of the conductive feature extends to contact the dielectric feature.

公开(公告)号：US20200312994A1

公开(公告)日：2020-10-01

申请号：US16441107

申请日：2019-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

公开(公告)号：US10755977B2

公开(公告)日：2020-08-25

申请号：US16222640

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Wei-Hao Wu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, a gate stack, a gate spacer, a conductive feature, and a conductive cap. The substrate has a source/drain region. The gate stack is on the substrate. The gate spacer is alongside the gate stack. The conductive feature is on the source/drain region. The conductive cap is on the conductive feature and has a top in a position lower than a top of the gate spacer.

公开(公告)号：US10720514B2

公开(公告)日：2020-07-21

申请号：US16104372

申请日：2018-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Wai-Yi Lien ,  Gwan-Sin Chang ,  Yu-Ming Lin ,  Ching Hsueh ,  Jia-Chuan You ,  Chia-Hao Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor fin, a first gate stack, and a first metal element-containing dielectric mask. The semiconductor fin protrudes from the substrate. The first gate stack is over the semiconductor fin. The first metal element-containing dielectric mask is over the first gate stack.

公开(公告)号：US20200168555A1

公开(公告)日：2020-05-28

申请号：US16597205

申请日：2019-10-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/532 ,  H01L29/78 ,  H01L29/417 ,  H01L23/522 ,  H01L21/768 ,  H01L29/40

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

公开(公告)号：US10651085B2

公开(公告)日：2020-05-12

申请号：US15719395

申请日：2017-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao Chang ,  Jia-Chuan You ,  Yu-Ming Lin ,  Chih-Hao Wang ,  Wai-Yi Lien

IPC: H01L29/76 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165

Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole, and forming a conductive structure in the hole.

公开(公告)号：US10269636B2

公开(公告)日：2019-04-23

申请号：US15605995

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Wai-Yi Lien ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L23/535 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first spacer, a second spacer, and a first contact plug. The gate structure is disposed on the semiconductor substrate. The first spacer is disposed around the gate structure. The second spacer is disposed on the first spacer. The first contact plug lands on the second spacer and the gate structure.