公开(公告)号：US09755983B1

公开(公告)日：2017-09-05

申请号：US14521435

申请日：2014-10-22

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: H04L12/801

CPC classification number: H04L47/39

Abstract: An apparatus and method for providing minipacket flow control. A device includes a traffic manager interface (TMI) circuit that receives a minipacket, communicates the minipacket to a physical layer circuit, and communicates a minipacket flow control signal to a scheduler circuit that controls if another minipacket is to be sent to the TMI circuit. In one example, upon receiving a minipacket the TMI circuit updates a current credit value, compares the current credit value with a credit limit value, and outputs a minipacket flow control signal that is a function of the comparison. In another example, upon receiving a minipacket the TMI circuit updates a current credit value, compares the current credit value with a credit limit value, reads and compares a credit pool value with a credit pool limit value, and outputs a minipacket flow control signal that is a function of both of the comparisons.

公开(公告)号：US09755948B1

公开(公告)日：2017-09-05

申请号：US14841723

申请日：2015-09-01

Applicant: Netronome Systems, Inc.

Inventor： Nicolaas J. Viljoen

IPC: H04J14/00 ,  H04L12/801 ,  H04L12/751 ,  H04Q11/00 ,  H04L12/851 ,  H04L12/24

CPC classification number: H04L45/08 ,  H04L41/0823 ,  H04L41/083 ,  H04L41/14 ,  H04L41/16 ,  H04L45/10 ,  H04L47/2483 ,  H04Q11/00 ,  H04Q11/0005 ,  H04Q11/0066 ,  H04Q2011/0079 ,  H04Q2213/13523

Abstract: A flow of packets is communicated through a data center including an electrical switch, an optical switch, and multiple racks each including multiple network devices. The optical switch can be controlled to receive packet traffic from a network device via a first optical link and to output that packet traffic to another network device via a second optical link. One network device includes a neural network that analyzes received packets of the flow. The optical switch is controlled to switch based on a result of the analysis performed. In one instance, the optical switch is controlled such that immediately prior to the switching no packet traffic passes from the first optical link and through the optical switch and to the second optical link but such that after the switching packet traffic does pass from the first optical link and through the optical switch and to the second optical link.

公开(公告)号：US09729442B1

公开(公告)日：2017-08-08

申请号：US14634848

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L12/931 ,  H04L12/947

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25 ,  H04L49/35

Abstract: A method of Software-Defined Networking (SDN) switching. A packet of a flow is received onto a SDN switch via a NFX circuit. The NFX circuit determines that the packet matches a flow entry stored in any flow table in the NFX circuit, counts the number of packets of the flow received, and determines that the number of packets of the flow received is above a threshold value. The NFX circuit then forwards the packet to a NFP circuit in the SDN switch. The NFP circuit determines that the packet matches a flow entry stored in the flow table in the NFX and generates a new flow entry that applies to a relatively narrow subflow of packets that is forwarded to and stored the flow table in the NFX circuit. A subsequent packet of the flow is switched by the SDN switch without forwarding the packet to the NFP.

公开(公告)号：US09727512B1

公开(公告)日：2017-08-08

申请号：US14530758

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: G06F13/36 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/4027 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0683

Abstract: A method of performing an identical packet multicast packet ready command (common packet multicast mode operation) is described herein. A packet ready command is received from a first memory system via a bus and onto a network interface circuit. The packet ready command includes a multicast value. A communication mode is determined as a function of the multicast value. The multicast value indicates a single packet is to be communicated by the network interface circuit to a first number of destinations. A free packet command is output from the network interface circuit onto the bus. The free packet command includes a Free On Last Transfer (FOLT) value that indicates that the packet will not be freed from the first memory system by the network interface circuit once the packet is transmitted. The network interface circuit and the memory system are included on an Island-Based Network Flow Processor.

公开(公告)号：US09703739B2

公开(公告)日：2017-07-11

申请号：US14590920

申请日：2015-01-06

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/4221

Abstract: In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

公开(公告)号：US09641466B2

公开(公告)日：2017-05-02

申请号：US14507643

申请日：2014-10-06

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: H04L12/861

CPC classification number: H04L49/9084

Abstract: A method for receiving a packet descriptor including a priority indicator and a queue number indicating a queue stored within a first memory unit, storing a packet associated with the packet descriptor in a second memory, determining a first amount of free memory in the first memory unit, determining if the first amount of free memory is above a threshold value, writing the packet from the second memory to a third memory when the first amount of memory is above the threshold value and the priority indicator is equal to a first value, not writing the packet from the second memory unit to the third memory unit if the first amount of memory is below the threshold value or when the priority indicator is equal to a second value. The priority indicator is equal to a first value for high priority packets and a second value for low priority packets.

公开(公告)号：US09641448B1

公开(公告)日：2017-05-02

申请号：US14611231

申请日：2015-01-31

Applicant: Netronome Systems, Inc.

Inventor： Christopher A. Telfer

IPC: H04L12/863 ,  H04L12/721

CPC classification number: H04L47/624 ,  H04L45/38 ,  H04L47/34

Abstract: An Island-Based Network Flow Processor (IB-NFP) receives packets of many flows, and classifies them as belonging to an ordering context. These packets are distributed to a set of Worker Processors (WPs), so that each packet of the context is processed by one WP, but multiple WPs operate on packets of the context at a given time. The WPs use an atomic ticket release functionality of a transactional memory to assist in determining when to release packets to another set of Output Processors (OP). The packets are indicated to the set of OPs in the correct order, even though the WPs may complete their processing of the packets in an out-of-order fashion. For a packet that is indicated as to be released, an OP generates a “transmit command” such that the packet (or a descriptor of the packet) is then put into a properly ordered stream for output from the IB-NFP.

公开(公告)号：US09632959B2

公开(公告)日：2017-04-25

申请号：US14326388

申请日：2014-07-08

Applicant: Netronome Systems, Inc.

Inventor： Rick Bouley

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/1663

Abstract: An efficient search key processing method includes writing a first and a second search key data set to a memory, where the search key data sets are written to memory on a word by word basis. Each of the first and second search key data sets includes a header indicating a common lookup operation to be performed and a string of search keys. The header is immediately followed in memory by a search key. The search keys are located contiguously in the memory. At least one word contains search keys from the first and second search key data sets. The memory is read word by word. A first plurality of lookup command messages are sent based on the search keys included in the first search key data set. A second plurality of lookup command messages are sent based on the search keys included in the second search key data set.

公开(公告)号：US09612981B2

公开(公告)日：2017-04-04

申请号：US13399324

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F13/00 ,  G06F13/14

CPC classification number: G06F13/4068 ,  G06F13/14 ,  G06F13/36 ,  G06F13/4022 ,  G06F17/5068

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.

公开(公告)号：US09594702B2

公开(公告)日：2017-03-14

申请号：US14326367

申请日：2014-07-08

Applicant: Netronome Systems, Inc.

Inventor： Rick Bouley

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1663 ,  G06F13/28

Abstract: A multi-processor includes a shared memory that stores a search key data set including multiple search keys, a processor, a Direct Memory Access (DMA) controller, and an Interlaken Look-Aside (ILA) interface circuit. The processor generates a descriptor that is sent to the DMA controller causing the DMA controller to read the search key data set. The DMA controller selects a single search key from the set and generates a lookup command message that is communicated to the ILA interface circuit. The ILA interface circuit generates an ILA packet that includes the single search key and sends the ILA packet to an external transactional memory device that generates a result data value. The result data value is communicated back to the DMA controller via the ILA interface circuit. The DMA controller stores the result data value in the shared memory and notifies the processor that the DMA process has completed.

Abstract translation: 多处理器包括共享存储器，其存储包括多个搜索键的搜索关键字数据集，处理器，直接存储器访问（DMA）控制器和因特拉肯后视（ILA）接口电路）。 处理器产生一个发送到DMA控制器的描述符，使DMA控制器读取搜索关键字数据集。 DMA控制器从集合中选择单个搜索关键字，并生成传送到ILA接口电路的查找命令消息。 ILA接口电路生成包括单个搜索密钥的ILA分组，并将ILA分组发送到产生结果数据值的外部事务存储器设备。 结果数据值通过ILA接口电路传回DMA控制器。 DMA控制器将结果数据值存储在共享存储器中，并通知处理器DMA进程已完成。