Abstract:
A method of operating a speaker system including a speaker coupled to an amplifier, and a dedicated digital speaker protection circuit includes turning on the amplifier in a mute mode, after a first delay period, issuing a play command to the amplifier to place the amplifier in a play mode, but without an input signal during a second delay period, and performing a speaker offset detection during the second delay period, wherein, if there is an offset, then the amplifier is forced back into the mute mode, and if there is no offset, then the amplifier is allowed to continue to operate in the play mode. The method also includes issuing a speaker protection control signal or command if an offset is detected.
Abstract:
A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.
Abstract:
A constant-frequency current-mode-controlled boost converter circuit provides slope compensation of an inductor current, reduces reverse inductor current in light output load conditions, and reduces oscillation between a discontinuous current mode and a continuous current mode by enabling or disabling an inductor current threshold. The constant-frequency current-mode-controlled boost converter circuit is efficient and stable in light, medium, and heavy output load conditions.
Abstract:
A device and method for detecting a short circuit in an electrical component during a start-up routine. In an embodiment, a device may have a problematic display having a short circuit that may result in damage to other components of the device if the device were allowed to fully startup during a normal start-up routine. Thus, power supplied to the panel may be initiated in stages so as to monitor any current that may be flowing through the panel, which in turn, may be indicative of a short circuit in the panel. If enough “leakage” current is detected through the panel during this staged startup routine, then a short-circuit detection circuit may interrupt the startup routine and lock out the operation of the device until the detected short circuit in the panel can be addressed.
Abstract:
A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.
Abstract:
An LIN transmitter includes a current mirror coupled to a transmit output node and a control circuit coupled to a transmit input node for controlling the current mirror with various load current control signals.
Abstract:
A boost converter circuit receives an input power supply voltage and produces an output boosted supply voltage. The circuit includes a voltage regulator, boosting circuitry, and a timing controller. The voltage regulator provides a regulated voltage to the boosting circuitry, which controls switching a transistor to drive the output boosted supply voltage; and the timing controller controls switching the boost circuit from the start-up mode to the normal operation mode. In start-up mode, the regulated voltage is generated from the input power supply voltage. During normal operation mode, the regulated voltage is generated from the output boosted supply voltage. The circuitry performs a low-power start-up when the input power supply voltage is low, and maintains efficient low-power operation by driving the transistor to produce the output boosted supply voltage as the input power supply voltage decreases.
Abstract:
Systems and methods are disclosed for determining the perceptibility of noise in a block of images and/or video. The systems and methods may compute a mask value for the block using a block masking generator. The mask value may indicate the perceptibility of noise in the block. The mask value may be computed using a normalized activity value and/or a texture value for the block. The normalized activity value may indicate the relative activity in the block as compared to the activity in the image and/or video. The texture value may indicate the strength and/or number of edges in the block.
Abstract:
An integrated circuit includes a bandgap reference generator and a voltage regulator. The bandgap reference generator includes a first current path, and a first bipolar transistor with an emitter-collector path in the first current path. The voltage regulator includes a second current path, wherein the second current path mirrors the first current path; a resistor configured to receive a current of the second current path; a second bipolar transistor with a base and a collector of the second bipolar transistor being interconnected; and a third bipolar transistor connected in series with the second bipolar transistor and the resistor. A base and a collector of the third bipolar transistor are interconnected.
Abstract:
A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.