公开(公告)号：US11063429B2

公开(公告)日：2021-07-13

申请号：US15951806

申请日：2018-04-12

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Radhakrishnan Sithanandam ,  Divya Agarwal ,  Ghislain Troussier ,  Jean Jimenez ,  Malathi Kar

IPC: H02H9/04 ,  H01L27/02

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.

公开(公告)号：US20210184691A1

公开(公告)日：2021-06-17

申请号：US17099423

申请日：2020-11-16

Applicant: STMicroelectronics International N.V.

Inventor： Vivek TRIPATHI

IPC: H03M1/74 ,  H03M1/76 ,  H03M3/00 ,  H03M7/16 ,  H03F3/45 ,  G06G7/186

Abstract: A quad signal generator circuit generates four 2N−1 bit control signals in response to a sampling clock and a 2N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2N−1 bit control signals. Outputs of the 2N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2N−1 bit control signals such that all logic states of bits of the four 2N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N−1 bit thermometer coded signal.

公开(公告)号：US20210151977A1

公开(公告)日：2021-05-20

申请号：US17095652

申请日：2020-11-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Manoj KUMAR ,  Ravinder KUMAR ,  Nicolas DEMANGE

IPC: H02H3/20 ,  H02H1/00

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

公开(公告)号：US20210143151A1

公开(公告)日：2021-05-13

申请号：US17152272

申请日：2021-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar SHARMA

IPC: H01L27/092 ,  H01L29/06

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

公开(公告)号：US20210135681A1

公开(公告)日：2021-05-06

申请号：US17089090

申请日：2020-11-04

Applicant: STMicroelectronics International N.V.

Inventor： Gagan MIDHA ,  Kallol CHATTERJEE

IPC: H03M3/00 ,  H03K7/08

Abstract: A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.

公开(公告)号：US10998721B2

公开(公告)日：2021-05-04

申请号：US15908878

申请日：2018-03-01

Applicant: STMicroelectronics International N.V.

Inventor： Radhakrishnan Sithanandam

IPC: H02H9/04 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L27/12 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L29/739 ,  H01L29/87 ,  H01L29/73 ,  H01L49/02

Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

公开(公告)号：US20210081174A1

公开(公告)日：2021-03-18

申请号：US16988912

申请日：2020-08-10

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F7/548 ,  H03K3/037 ,  H03K5/01 ,  G06F7/544

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

公开(公告)号：US20210065776A1

公开(公告)日：2021-03-04

申请号：US16994488

申请日：2020-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Anuj GROVER ,  Tanmoy ROY

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C5/02

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

公开(公告)号：US20210044971A1

公开(公告)日：2021-02-11

申请号：US16531587

申请日：2019-08-05

Applicant: STMicroelectronics International N.V.

Inventor： Prashant Pandey ,  Salil Jain ,  Alok Kumar Mittal

IPC: H04W12/04 ,  H04W12/00 ,  H04L9/32

Abstract: In accordance with embodiments, methods for the recovery of security credentials of a Bluetooth mesh network are disclosed. A computing device of the Bluetooth mesh network receives user login information, and generates a network key of the Bluetooth mesh network based on the user login information. The computing device generates an application key of a first node to be provisioned based on user login information. A device key is generated using the unicast address of the first node and part of user credentials. The current sequence number is recovered by one of the four techniques depending on the characteristics of the network. The unicast addresses of the nodes are assumed to be sequential and later validated by sending messages. IV index is recovered using processes defined in the Bluetooth mesh standard. After recovery of the above parameters, the mesh network can operate normally using the aforementioned computing device.

公开(公告)号：US20200333399A1

公开(公告)日：2020-10-22

申请号：US16387809

申请日：2019-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Shiv Kumar VATS ,  HIMANSHU

IPC: G01R31/3185 ,  G01R31/3187 ,  G01R31/3183

Abstract: A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.