Abstract:
An approach is provided that allows an administrator to set a new password at a wireless access point, such as a traditional WAP or a wireless router. The wireless access point creates a message that includes the new password. The message is encrypted using the old password that was previously set for the wireless network. The encrypted message is wirelessly transmitted from the wireless access point to the active client devices (those clients currently accessing the wireless network). The clients decrypt the message using the old password that was previously provided to the clients. The clients retrieve the new password from the message. The clients construct a new message that is encrypted using the new password. The new message is wirelessly transmitted from the clients to the wireless access device and serves as an acknowledgement.
Abstract:
An optimization engine includes a mixed-integer programming (MIP) solver that receives a programming model, an outcome objective, and a group of start vectors. Each of the MIP start vectors in the group specify one or more restrictions to apply to the programming model. The MIP solver uses the programming model to compute a potential solution from each of the MIP start vectors included in the group, which results in a group of potential solutions. Next, the MIP solver selects one of the potential solutions in the group as an optimal intra-group solution. The optimal intra-group solution is the potential solution in the group that best achieves the outcome objective. In turn, the optimal intra-group solution is used to complete the outcome objective.
Abstract:
The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
Abstract:
An approach is provided that receives web page data at a network adapter included in an information handling system. A process identifies a first set style sheets that apply to the web page data and a second set of style sheets that apply to graphical elements that are within a predefined proximity area of a cursor that is displayed on the information handling system's display screen. The process displays graphical elements that are outside the predefined proximity area using the first set of style sheets and simultaneously displays a second set of elements that are within the predefined proximity area using the second set of style sheets.
Abstract:
Non-invasive collection of data is presented. A server segments a web page into regions and sends the segmented web page along with a data collector program to a client in response to receiving a client request. The client displays the web page and loads the data collector program which initiates particular event handlers to monitor user event activity corresponding to the displayed web page. When the user performs a user event, such as moving his mouse into a particular web page region, the data collector program collects user event data and associates the user event data with the particular web page region. When the user event is complete, the data collector program sends the collected user event data to the server.
Abstract:
A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.
Abstract:
A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best electromigration quality value is selected. In one embodiment, each routing is analyzed with attention to the current that passes through each of the routing's segments in order to compute a current distribution that is used to compute a routing quality vector. In another embodiment, multiple placements are generated and the electromigration placement quality vectors are computed for the various placements with the placement with the best electromigration quality vector being selected. In one embodiment, the placement with the best electromigration quality vector is routed the number of times to determine the routing with the lowest (best) electromigration quality value.
Abstract:
An approach to optimize specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process. In one embodiment, the invention may be implemented using PowerPC™ assembly and VMX™ or Altivec™ instructions. In this embodiment, the intensity instruction may be represented as a “vspecefp” instruction, which stands for a “vector specular estimate floating point” instruction.
Abstract:
A method is presented that handles a power down signal received by a device. Other types of signals, such as suspend or save and sleep, may also be handled. A device, such as a parent device, sends a power down signal to another device, such as a child device. The power down signal is received by the child device and acted upon, based on the activities currently being executed by the child device. Each activity currently being executed by the child device is handled according to its corresponding setting in an activity list. For example, if the child device is currently executing a preferred activity, the power down signal is ignored. A user of the child device may also send an explanation (or explanations) to the parent device.
Abstract:
A method for providing an alternate keypad arrangement in a virtual keypad is presented. In the alternate keypad arrangement, the virtual keys are laid out in a non-sequential arrangement. In one embodiment, the labels displayed on the virtual keys appear sequential, however the values registered when the user presses the virtual key does not match the label and, hence, the values are laid out in a non-sequential manner. Using alternate keypad arrangements arranged in patterns enables the user to use a common pattern, or patterns easily remembered by the user, for a wide variety of authentication data used to access a wide variety of systems. Rather than remembering the specific PIN codes and passwords, the user simply remembers a pattern and selects virtual keys that match the pattern.